diff --git a/bin/lint-wally b/bin/lint-wally index cc658edc6..dd28f4677 100755 --- a/bin/lint-wally +++ b/bin/lint-wally @@ -26,7 +26,10 @@ fi for config in ${configs[@]}; do # echo "$config linting..." - if !($verilator --lint-only --quiet --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --lint-only --quiet --top-module wallywrapper \ + "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \ + $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \ + -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" fails=$((fails+1)) @@ -48,4 +51,5 @@ echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings" # -I points to the include directory where files such as `include config.vh are found # For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command +# verilator --lint-only -Wall --quiet --top-module wallywrapper -Iconfig/shared -Iconfig/rv64gc src/cvw.sv testbench/wallywrapper.sv src/*/*.sv src/*/*/*.sv -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist. diff --git a/bin/regression-wally b/bin/regression-wally index f85800bba..add2bd24a 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -423,6 +423,7 @@ def main(): """Run the tests and count the failures""" global configs, coverage os.chdir(regressionDir) + os.system('rm -rf questa/wkdir') for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]: try: os.mkdir(d) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 44ff08aee..cf2ff9cce 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -112,7 +112,6 @@ make install # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g cd $RISCV git clone https://github.com/verilator/verilator # Only first time # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 5e3a2e419..44bf77eac 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -110,20 +110,10 @@ localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : B localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN)); localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1)); -// size of FMA output +// size of FMA output in U(NF+4).(3NF+2) format localparam FMALEN = 3*NF + 6; // NORMSHIFTSIZE is the bits out of the normalization shifter -// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75 -// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89 -// RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162 -// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing for fcvt.lu.s -// with CVTLEN+NF+1. Changing to CVTLEN+NF+1+2 fixes failures -// This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64 -// because NORMSHIFTSZ becomes limited by convert rather than divider -// The two extra bits are necessary because shiftcorrection dropped them for fcvt. -// May be possible to remove these two bits by modifying shiftcorrection -//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index e7b8f1abc..597907a8e 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -86,7 +86,7 @@ INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ") INCLUDE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +incdir+../../tests +define+ +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" # Prepare RTL files avoiding certain paths -RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_512x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" +RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" # Simulation and Coverage Commands OUTPUT="sim_out" diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c index 6589a3848..572acaa55 100644 --- a/sim/verilator/wrapper.c +++ b/sim/verilator/wrapper.c @@ -3,5 +3,9 @@ #include "Vtestbench__Dpi.h" const char *getenvval(const char *pszName) { + const char *pszValue = getenv(pszName); + if (pszValue == NULL) { + return ""; + } return ((const char *) getenv(pszName)); } \ No newline at end of file diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 53d43a6b3..44966f03c 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -7,7 +7,7 @@ // // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -87,14 +87,13 @@ module cache import cvw::*; #(parameter cvw_t P, logic LineDirty, HitLineDirty; logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] Tag; - logic [SETLEN-1:0] FlushAdr, NextFlushAdr, FlushAdrP1; + logic [SETLEN-1:0] FlushAdr; logic FlushAdrCntEn, FlushCntRst; logic FlushAdrFlag, FlushWayFlag; logic [NUMWAYS-1:0] FlushWay, NextFlushWay; logic FlushWayCntEn; logic SelWriteback; logic LRUWriteEn; - logic ResetOrFlushCntRst; logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic SelFetchBuffer; logic CacheEn; @@ -128,7 +127,7 @@ module cache import cvw::*; #(parameter cvw_t P, if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag, .LRUWriteEn, - .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); + .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else assign VictimWay = 1'b1; // one hot. @@ -201,6 +200,9 @@ module cache import cvw::*; #(parameter cvw_t P, ///////////////////////////////////////////////////////////////////////////////////////////// if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed + logic ResetOrFlushCntRst; + logic [SETLEN-1:0] NextFlushAdr, FlushAdrP1; + // Flush address (line number) assign ResetOrFlushCntRst = reset | FlushCntRst; flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr); diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 3cbadd530..79b277a03 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -7,7 +7,7 @@ // // Purpose: Implements Pseudo LRU. Tested for Powers of 2. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -40,7 +40,6 @@ module cacheLRU input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set - input logic ClearValid, // Clear the dirty bit in the selected way and set input logic InvalidateCache, // Clear all valid bits output logic [NUMWAYS-1:0] VictimWay // LRU selects a victim to evict ); @@ -48,12 +47,12 @@ module cacheLRU localparam LOGNUMWAYS = $clog2(NUMWAYS); logic [NUMWAYS-2:0] LRUMemory [NUMSETS-1:0]; - logic [NUMWAYS-2:0] CurrLRU; - logic [NUMWAYS-2:0] NextLRU; + logic [NUMWAYS-2:0] CurrLRU, NextLRU, ReadLRU, BypassedLRU; logic [LOGNUMWAYS-1:0] HitWayEncoded, Way; logic [NUMWAYS-2:0] WayExpanded; logic AllValid; - + logic ForwardLRU; + genvar row; /* verilator lint_off UNOPTFLAT */ @@ -131,29 +130,22 @@ module cacheLRU assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end - priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero); binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay); mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc); decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay); - // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice. - // This is a two port memory. - // Every cycle must read from CacheSetTag and each load/store must write the new LRU. - - // note: Verilator lint doesn't like <= for array initialization (https://verilator.org/warn/BLKLOOPINIT?v=5.021) - // Move to = to keep Verilator happy and simulator running fast - always_ff @(posedge clk) begin + // LRU memory must be reset for Questa to run. The reset value does not matter but it is best to be deterministc. + always_ff @(posedge clk) if (reset | (InvalidateCache & ~FlushStage)) - for (int set = 0; set < NUMSETS; set++) LRUMemory[set] = '0; // exclusion-tag: initialize - else if(CacheEn) begin - // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value - if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU; - else CurrLRU = LRUMemory[CacheSetTag]; - if(LRUWriteEn) LRUMemory[PAdr] = NextLRU; - end - end + for (int set = 0; set < NUMSETS; set++) LRUMemory[set] <= '0; // exclusion-tag: initialize + else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU; + // LRU read path with write forwarding + assign ReadLRU = LRUMemory[CacheSetTag]; + assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag); + mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU); + flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU); endmodule diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d3cff2e96..64084f863 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for the cache fsm // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 41e620547..fb9d39f41 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -7,7 +7,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -76,7 +76,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic ClearValidWay; logic SetDirtyWay; logic ClearDirtyWay; - logic SelNonHit; logic SelectedWay; logic InvalidateCacheDelay; diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 95920ec7e..3e9718c27 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -7,7 +7,7 @@ // // Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes. // -// Documentation: RISC-V System on Chip Design Chapter 7 +// Documentation: RISC-V System on Chip Design // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index f033b40cc..2e6973ba5 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions. // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -79,8 +79,7 @@ module ahbcacheinterface import cvw::*; #( logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -114,11 +113,14 @@ module ahbcacheinterface import cvw::*; #( .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec - // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. - // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - - flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); + if (READ_ONLY_CACHE) begin + assign HWSTRB = '0; + end else begin // compute byte mask for AHB transaction based on size and address. AHBW may be different than LLEN + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); + end buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 8852b52c3..a9bf8f497 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ). // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index b0f28966e..5f39e1602 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for cache to AHB bus interface // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 11ba896e4..8aa640673 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -7,7 +7,7 @@ // // Purpose: Simple NON_SEQ (no burst) AHB controller. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 67e4795a6..97ea0d5b4 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 1b6c0a1fa..2eec7db58 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -110,7 +110,7 @@ module ebu import cvw::*; #(parameter cvw_t P) ( .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY)); - // output mux //*** switch to structural implementation + // output mux assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0; assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 571bdcc63..daf3da1e8 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -8,7 +8,7 @@ // Purpose: Arbitrates requests from instruction and data streams // LSU has priority. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index f35f71869..6f52b0eae 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 0944090fc..d1baac3b8 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point comparison unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d8c1fe1d7..4f1bf042b 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index ad3a2f602..90e8d7a23 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point conversions of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // Int component of the Wally configurable RISC-V project. // @@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // shifter /////////////////////////////////////////////////////////////////////////// - // kill the shift if it's negative + // kill the shift if it is negative // select the amount to shift by // fp -> int: // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 @@ -201,10 +201,10 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // - shift left by LeadingZeros - to shift till the result is normalized // - only shift fp -> fp if the intital value is subnormal // - this is a problem because the input to the lzc was the fraction rather than the mantissa - // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? + // - rather have a few and-gates than an extra bit in the priority encoder??? always_comb if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}}; - else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; + else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; else ShiftAmt = LeadingZeros; /////////////////////////////////////////////////////////////////////////// diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index dba69267a..2824c860a 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -65,11 +65,9 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( logic WZeroE; // Early termination flag logic [P.DURLEN-1:0] CyclesE; // FSM cycles logic SpecialCaseM; // Divide by zero, square root of negative, etc. - logic DivStartE; // Enable signal for flops during stall // Integer div/rem signals logic BZeroM; // Denominator is zero - logic IntDivM; // Integer operation logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor @@ -80,8 +78,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( .FmtE, .Bias(BiasE), .Nf(NfE), .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE, // Int-specific .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE, - .BZeroM, .IntNormShiftM, .AM, - .IntDivM, .W64M, .ALTBM, .AsM, .BsM); + .BZeroM, .IntNormShiftM, .AM, .W64M, .ALTBM, .AsM, .BsM); fdivsqrtfsm #(P) fdivsqrtfsm( // FSM .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 9e2489eb3..2347c9d21 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -6,7 +6,7 @@ // // Purpose: Determine number of cycles for divsqrt // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -28,9 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) ( - input logic [P.FMTBITS-1:0] FmtE, input logic [P.LOGFLEN-1:0] Nf, // Number of fractional bits in selected format - input logic SqrtE, input logic IntDivE, input logic [P.DIVBLEN-1:0] IntResultBitsE, output logic [P.DURLEN-1:0] CyclesE diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 03d144263..058a3d17b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Exponent caclulation for divide and square root // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index bc9dce536..799ded999 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index a04523e58..90af95643 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8975edeb6..4e05b5e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: divsqrt state machine for multi-cycle operations // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 4bfcebcd1..dc6b0057a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: k stages of divsqrt logic, plus registers // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -44,7 +44,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb logic [P.DIVb+3:0] WC[P.DIVCOPIES:0]; // Q4.DIVb - logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb // *** probably Q not U. See Table 16.26 notes + logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb logic [P.DIVb:0] UM[P.DIVCOPIES:0]; // U1.DIVb logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.DIVb logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.DIVb diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index c3954bc0a..6a2830421 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root postprocessing // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -131,5 +131,6 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( W64M, FIntDivResultM); end else assign FIntDivResultM = IntDivResultM[P.XLEN-1:0]; - end + end else + assign FIntDivResultM = '0; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 802ac92dc..648018a5d 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -47,7 +47,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( output logic ISpecialCaseE, output logic [P.DURLEN-1:0] CyclesE, output logic [P.DIVBLEN-1:0] IntNormShiftM, - output logic ALTBM, IntDivM, W64M, + output logic ALTBM, W64M, output logic AsM, BsM, BZeroM, output logic [P.XLEN-1:0] AM ); @@ -58,7 +58,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result - logic NumerZeroE; // Numerator is zero (X or A) logic AZeroE, BZeroE; // A or B is Zero for integer division logic SignedDivE; // signed division logic AsE, BsE; // Signs of integer inputs @@ -96,11 +95,9 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // Select integer or floating point inputs mux2 #(P.DIVb+1) ifxmux({Xm, {(P.DIVb-P.NF){1'b0}}}, {PosA, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFX); mux2 #(P.DIVb+1) ifdmux({Ym, {(P.DIVb-P.NF){1'b0}}}, {PosB, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFD); - mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE); end else begin // Int not supported assign IFX = {Xm, {(P.DIVb-P.NF){1'b0}}}; assign IFD = {Ym, {(P.DIVb-P.NF){1'b0}}}; - assign NumerZeroE = XZeroE; end ////////////////////////////////////////////////////// @@ -147,7 +144,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign DivXShifted = DivX; end end else begin - assign ISpecialCaseE = 1'b0; + assign {ISpecialCaseE, IntResultBitsE} = '0; end ////////////////////////////////////////////////////// @@ -174,7 +171,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // 4 2(x)-4 = 4(x/2 - 1)) 2(x/2)-4 = 4(x/4 - 1) // Summary: PreSqrtX = r(x/2or4 - 1) - logic [P.DIVb:0] PreSqrtX; assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even @@ -215,21 +211,20 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM); // Number of FSM cycles (to FSM) - fdivsqrtcycles #(P) cyclecalc(.FmtE, .Nf, .SqrtE, .IntDivE, .IntResultBitsE, .CyclesE); + fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE); if (P.IDIV_ON_FPU) begin:intpipelineregs logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; logic RemOpE; /* verilator lint_off WIDTH */ - assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain + assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. n = (Cycles * k - 1) assign IntRemNormShiftE = mE + (P.DIVb-(P.XLEN-1)); // m + b - (N-1) for remainder normalization shift /* verilator lint_on WIDTH */ assign RemOpE = Funct3E[1]; mux2 #(P.DIVBLEN) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE); // pipeline registers - flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM); @@ -238,7 +233,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM); if (P.XLEN==64) flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); - end + end else + assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index c3d6e210c..fa13cadeb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: radix-2 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index 856273a5e..551a358c4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: radix-4 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -52,7 +52,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( // Digit Selection logic assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0 - assign j1 = C[P.DIVb] & ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; *** could simplify to ~C[P.DIVb-1] because j=0 case takes priority + assign j1 = ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; simplified from C[P.DIVb] & ~C[P.DIVb-1] because j=0 case takes priority assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1 assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 55810665b..db858cb0b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 5a802934e..3d842f9a8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index 2d4cd5e48..193231eea 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index 610b79395..840215c28 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -6,7 +6,7 @@ // // Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index fd1092497..e6eb45f75 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -47,7 +47,7 @@ module fdivsqrtuslc4cmp ( // Wmsbs = | | logic [6:0] mk2, mk1, mk0, mkm1; - logic [6:0] mkj2, mkj1, mkj0, mkjm1; + logic [6:0] mkj2, mkj1; logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0]; logic sqrtspecial; @@ -95,7 +95,7 @@ module fdivsqrtuslc4cmp ( // Choose A for current operation always_comb if (SqrtE) begin - if (Smsbs[4]) A = 3'b111; // for S = 1.0000 *** can we optimize away this case? + if (Smsbs[4]) A = 3'b111; // for S = 1.0000 else A = Smsbs[2:0]; end else A = Dmsbs; @@ -108,7 +108,7 @@ module fdivsqrtuslc4cmp ( /* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000 assign mk0 = -mk1; - assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path + assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table */ // Compare residual W to selection constants to choose digit @@ -117,5 +117,5 @@ module fdivsqrtuslc4cmp ( else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1 else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0 else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1 - else udigit = 4'b0001; // choose -2 + else udigit = 4'b0001; // choose -2 endmodule diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index e68934294..c31324ad1 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index cf3b736d7..349189f33 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point float immediate // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index 8bf4d4cbb..36d4a0ad5 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 995494f2c..4942f9d9f 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index c6f0afebc..292472f7f 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA alginment shift // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index 06ac7e290..4ad254f79 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 01439f4d1..417b9de28 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14) +// Documentation: RISC-V System on Chip Design // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 8ce492f03..ea0ea2238 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index 891c28746..8220f0aad 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fmtparams.sv b/src/fpu/fmtparams.sv index d83dfd782..ad2dcfa4d 100644 --- a/src/fpu/fmtparams.sv +++ b/src/fpu/fmtparams.sv @@ -7,7 +7,7 @@ // // Purpose: Look up bias of exponent and number of fractional bits for the selected format // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index ba986dadc..7619b92af 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -218,7 +218,6 @@ module fpu import cvw::*; #(parameter cvw_t P) ( {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10); - // ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z @@ -280,7 +279,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( logic [P.FLEN-1:0] FliResE; // Zfa Floating-point load immediate value // fround - fround #(P) fround(.X(XE), .Xs(XsE), .Xe(XeE), .Xm(XmE), + fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE), .XNaN(XNaNE), .XSNaN(XSNaNE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE), .ZfaFRoundNX(ZfaFRoundNXE), .FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE)); diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index e907875a2..40933de17 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index d905618ba..3265ec626 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point round to integer for Zfa // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -28,7 +28,6 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fround import cvw::*; #(parameter cvw_t P) ( - input logic [P.FLEN-1:0] X, // input before unpacking input logic Xs, // input's sign input logic [P.NE-1:0] Xe, // input's exponent input logic [P.NF:0] Xm, // input's fraction with leading integer bit (U1.NF) @@ -45,7 +44,7 @@ module fround import cvw::*; #(parameter cvw_t P) ( logic [P.NE-1:0] E, Xep1; logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd; - logic [P.FLEN-1:0] W, PackedW; + logic [P.FLEN-1:0] W; logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf; // Unbiased exponent diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 4fe03522b..68e2eb493 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv index c9a500700..e83f403c5 100644 --- a/src/fpu/packoutput.sv +++ b/src/fpu/packoutput.sv @@ -7,7 +7,7 @@ // // Purpose: Pack the output of the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -100,4 +100,4 @@ module packoutput import cvw::*; #(parameter cvw_t P) ( endcase end end -endmodule \ No newline at end of file +endmodule diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 19993a996..84f5120a0 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index d45afeea6..d46b58f35 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index cb16cc2a1..be28a490c 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index cf334aa9b..22c354e30 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index 5ca848b0b..b9cb038a4 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f235d4d5b..d0a14cbfd 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 2db03cb16..f4af9d440 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing: normalization, rounding, sign, flags, special cases // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -157,11 +157,11 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( end 2'b00: begin // cvt ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt}; - ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}}; + ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-(P.CVTLEN+P.NF+1){1'b0}}}; end 2'b01: begin //divsqrt ShiftAmt = DivShiftAmt; - ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}}; + ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-(P.DIVb+1+P.NF){1'b0}}}; end default: begin ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 69f25a2b0..9425ec7ee 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index c99d5185c..4c6d251fb 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 7eedc5eba..fe422b98c 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation for rounding // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index ad811a747..0524ca364 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -45,13 +45,12 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( output logic [P.NE+1:0] Ue // corrected exponent for divider ); - logic [P.NORMSHIFTSZ-1:0] CorrShifted; // the shifted sum after LZA correction logic ResSubnorm; // is the result Subnormal logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction logic LeftShiftQm; // should the divsqrt result be shifted one to the left logic RightShift; // shift right by 1 - // *** 4/16/24 this code is a mess and needs cleaning and explaining + // dh 4/16/24 this code is a mess and needs cleaning and explaining // define bit widths // seems to shift by 0, 1, or 2. right and left shift is confusing @@ -61,20 +60,20 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // - a one has to propagate all the way through a sum. so we can leave the bottom statement alone assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1]; - // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm) - assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - - assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; + assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - // one bit right shift for FMA or division - mux2 #(P.NORMSHIFTSZ) corrmux({Shifted[P.NORMSHIFTSZ-3:0], 2'b00}, {Shifted[P.NORMSHIFTSZ-2:1], 2'b00}, RightShift, CorrShifted); - + // Determine the shif for either FMA or divsqrt + assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; + + // possible one bit right shift for FMA or division // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits always_comb - if (FmaOp | (DivOp & ~DivResSubnorm)) Mf = CorrShifted; - else Mf = Shifted[P.NORMSHIFTSZ-1:0]; + if (FmaOp | (DivOp & ~DivResSubnorm)) // one bit shift for FMA or divsqrt + if (RightShift) Mf = {Shifted[P.NORMSHIFTSZ-2:1], 2'b00}; + else Mf = {Shifted[P.NORMSHIFTSZ-3:0], 2'b00}; + else Mf = Shifted[P.NORMSHIFTSZ-1:0]; // convert and subnormal division result // Determine sum's exponent // main exponent issues: diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index b9dbf4b9e..bb655942d 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 2e87d17fc..e0e35312f 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -46,23 +46,21 @@ module unpack import cvw::*; #(parameter cvw_t P) ( output logic [P.LOGFLEN-1:0] Nf // Number of fractional bits ); - logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero - logic XFracZero, YFracZero, ZFracZero; // is the fraction zero logic YExpMax, ZExpMax; // is the exponent all 1s unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive, - .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), + .NaN(XNaN), .SNaN(XSNaN), + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .Subnorm(XSubnorm), .PostBox(XPostBox)); unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive, - .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), + .NaN(YNaN), .SNaN(YSNaN), + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .Subnorm(), .PostBox()); unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive, - .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), + .NaN(ZNaN), .SNaN(ZSNaN), + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .Subnorm(), .PostBox()); // look up bias and fractional bits for the given format diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index a6c421e5c..c90ede41d 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -39,8 +39,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( output logic SNaN, // is the number a signaling NaN output logic Zero, // is the number zero output logic Inf, // is the number infinity - output logic ExpNonZero, // is the exponent not zero - output logic FracZero, // is the fraction zero output logic ExpMax, // does In have the maximum exponent (NaN or Inf) output logic Subnorm, // is the number subnormal output logic [P.FLEN-1:0] PostBox // Number reboxed correctly as a NaN @@ -48,6 +46,8 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( logic [P.NF-1:0] Frac; // Fraction of XYZ logic BadNaNBox; // incorrectly NaN Boxed + logic FracZero; // is the fraction zero + logic ExpNonZero; // is the exponent non-zero logic [P.FLEN-1:0] In; // Gate input when FPU is not active to save power and simulation diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index dc5f6450c..91e01c7ab 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -34,7 +34,7 @@ module aplusbeq0 #(parameter WIDTH = 8) ( logic [WIDTH-1:0] orshift; // The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns - // *** explain, cite book + // See J. A. Prabhu and G. Zyner, "167 MHz radix-8 divide and square root using overlapped radix-2 stages," IEEE Symp. Computer Arithmetic, 1995, pp. 155-162. assign x = a ^ b; assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0}; diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 78b816c3c..8af273fc5 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -29,8 +29,5 @@ module decoder #(parameter BINARY_BITS = 3) ( output logic [(2**BINARY_BITS)-1:0] onehot ); - // *** Double check whether this synthesizes as expected - // -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists assign onehot = 1 << binary; - endmodule diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index a0dd5aef4..d333048b7 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -44,11 +44,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE output logic [WIDTH-1:0] dout ); - bit [WIDTH-1:0] RAM[DEPTH-1:0]; - - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // TRUE SRAM macro - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; // 64 x 128-bit SRAM @@ -79,11 +77,11 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// end else begin: ram - integer i; + bit [WIDTH-1:0] RAM[DEPTH-1:0]; if (PRELOAD_ENABLED) begin initial begin @@ -103,11 +101,13 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE // Write divided into part for bytes and part for extra msbs // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Therefore these always blocks use the older always @(posedge clk) - if(WIDTH >= 8) + if(WIDTH >= 8) begin + integer i; always @(posedge clk) if (ce & we) for(i = 0; i < WIDTH/8; i++) if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8]; + end if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index a030d2aab..cdca14e38 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -41,11 +41,9 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( output logic [WIDTH-1:0] dout ); - bit [WIDTH-1:0] RAM[DEPTH-1:0]; - - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// // TRUE SRAM macro - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), @@ -64,13 +62,14 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( .A(addr), .D(din), .BWEB('0), .Q(dout)); - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// end else begin: ram - // *** Vivado is not implementing this as block ram for some reason. + // Vivado is not implementing this as block ram for some reason. // The version with byte write enables it correctly infers block ram. - integer i; + + bit [WIDTH-1:0] RAM[DEPTH-1:0]; // Combinational read: register address and read after clock edge logic [$clog2(DEPTH)-1:0] addrd; diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index c4cee8b7e..196aa0875 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -44,13 +44,12 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) output logic [WIDTH-1:0] rd1 ); - bit [WIDTH-1:0] mem[DEPTH-1:0]; localparam SRAMWIDTH = 32; localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; - // *************************************************************************** - // TRUE Smem macro - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// + // TRUE SRAM macro + /////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin @@ -105,39 +104,35 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) .QA(SRAMReadData), .QB()); - end else begin + end else begin:ram - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** - integer i; -/* - initial begin // initialize memory for simulation only; not needed because done in the testbench now - integer j; - for (j=0; j < DEPTH; j++) - mem[j] = '0; - end -*/ + /////////////////////////////////////////////////////////////////////////////// + + bit [WIDTH-1:0] RAM[DEPTH-1:0]; // Read logic [$clog2(DEPTH)-1:0] ra1d; flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); - assign rd1 = mem[ra1d]; + assign rd1 = RAM[ra1d]; // Write divided into part for bytes and part for extra msbs // coverage off // when byte write enables are tied high, the last IF is always taken - if(WIDTH >= 8) + if(WIDTH >= 8) begin + integer i; always @(posedge clk) if (ce2 & we2) for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8]; + if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8]; + end // coverage on if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8]; + RAM[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8]; end endmodule diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_2048x64.sv similarity index 100% rename from src/generic/mem/ram2p1r1wbe_512x64.sv rename to src/generic/mem/ram2p1r1wbe_2048x64.sv diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 5d2611dda..a5b6e319d 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine stalls and flushes // -// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/aes/aes64ks1i.sv b/src/ieu/aes/aes64ks1i.sv index 3c1d203f9..cb2d71018 100644 --- a/src/ieu/aes/aes64ks1i.sv +++ b/src/ieu/aes/aes64ks1i.sv @@ -26,11 +26,11 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aes64ks1i( - input logic [3:0] round, - input logic [63:0] rs1, - input logic [31:0] Sbox0Out, - output logic [31:0] SboxKIn, - output logic [63:0] result + input logic [3:0] round, + input logic [63:32] rs1, + input logic [31:0] Sbox0Out, + output logic [31:0] SboxKIn, + output logic [63:0] result ); logic finalround; diff --git a/src/ieu/aes/aes64ks2.sv b/src/ieu/aes/aes64ks2.sv index dac9ed50d..b5209d799 100644 --- a/src/ieu/aes/aes64ks2.sv +++ b/src/ieu/aes/aes64ks2.sv @@ -26,9 +26,9 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aes64ks2( - input logic [63:0] rs2, - input logic [63:0] rs1, - output logic [63:0] result + input logic [63:0] rs2, + input logic [63:32] rs1, + output logic [63:0] result ); logic [31:0] w0, w1; diff --git a/src/ieu/aes/aesinvshiftrows64.sv b/src/ieu/aes/aesinvshiftrows64.sv index c934116ac..7e24f67c8 100644 --- a/src/ieu/aes/aesinvshiftrows64.sv +++ b/src/ieu/aes/aesinvshiftrows64.sv @@ -26,7 +26,9 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aesinvshiftrows64( - input logic [127:0] a, + /* verilator lint_off UNUSEDSIGNAL */ + input logic [127:0] a, + /* verilator lint_on UNUSEDSIGNAL */ output logic [63:0] y ); diff --git a/src/ieu/aes/aesshiftrows64.sv b/src/ieu/aes/aesshiftrows64.sv index 7c8a68120..11577bf3a 100644 --- a/src/ieu/aes/aesshiftrows64.sv +++ b/src/ieu/aes/aesshiftrows64.sv @@ -26,7 +26,9 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aesshiftrows64( + /* verilator lint_off UNUSEDSIGNAL */ input logic [127:0] a, + /* verilator lint_on UNUSEDSIGNAL */ output logic [63:0] y ); diff --git a/src/ieu/aes/aesshiftrows64.xv b/src/ieu/aes/aesshiftrows64.xv deleted file mode 100644 index 58638cea5..000000000 --- a/src/ieu/aes/aesshiftrows64.xv +++ /dev/null @@ -1,35 +0,0 @@ -/////////////////////////////////////////// -// aesshiftrows64.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: aesshiftrow for taking in first Data line -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module aesshiftrows64( - input logic [127:0] a, - output logic [63:0] y -); - - assign y = {a[31:24], a[119:112], a[79:72], a[39:32], - a[127:120], a[87:80], a[47:40], a[7:0]}; -endmodule diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 74eb6f7f6..e142de1e7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 76734f97f..4caee782a 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -49,7 +49,6 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] ZBBResult; // ZBB Result logic [P.XLEN-1:0] ZBCResult; // ZBC Result logic [P.XLEN-1:0] ZBKBResult; // ZBKB Result - logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result logic [P.XLEN-1:0] ZKNDEResult; // ZKNE or ZKND Result @@ -93,7 +92,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZBC and ZBKCUnit if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc - zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); + zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3(Funct3[1:0]), .ZBCResult); end else assign ZBCResult = '0; // ZBB Unit @@ -108,7 +107,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZBKB Unit if (P.ZBKB_SUPPORTED) begin: zbkb - zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); + zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU[P.XLEN/2-1:0]), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); end else assign ZBKBResult = '0; // ZBKX Unit @@ -125,7 +124,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZKNH Unit if (P.ZKNH_SUPPORTED) begin: zknh if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); - else zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + else zknh64 ZKNH64(.A(ABMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); end else assign ZKNHResult = '0; // Result Select Mux diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 083033d53..5fc4e8b49 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -7,7 +7,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 97a0caa45..fb4e603c0 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -31,11 +31,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Decode stage control signals - input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage input logic ALUOpD, // Regular ALU Operation - output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage - output logic [3:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage @@ -46,7 +43,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( output logic [2:0] ALUSelectD, // ALU select output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [3:0] ZBBSelectE, // ZBB mux select signal - output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE // Bit manipulation instruction being executed ); @@ -61,6 +57,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( logic [2:0] BALUControlD; // ALU Control signals for B instructions logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage + logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + logic [3:0] ZBBSelectD; // ZBB mux select signal in Decode stage `define BMUCTRLW 20 @@ -285,5 +283,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); // BMU Execute stage pipieline control register - flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); + flopenrc #(12) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BALUControlE, BMUActiveE}); endmodule diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 263680aea..33a0dc332 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index f32fcece9..2ea45606f 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index dff468257..f0bc5f72d 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -7,7 +7,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 66d69fb21..c5dcbf531 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -7,7 +7,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module ext #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, // Operands + input logic [15:0] A, // Operand to extend input logic [1:0] ExtSelect, // B[2], B[0] of immediate output logic [WIDTH-1:0] ExtResult); // Extend Result diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 838468fa1..435c8dff1 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -5,7 +5,7 @@ // // Purpose: Population Count // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f9957c787..d5ca3bd4b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -46,7 +46,7 @@ module zbb #(parameter WIDTH=32) ( mux2 #(1) ltmux(LT, LTU, BUnsigned , lt); cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); - ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); + ext #(WIDTH) ext(.A(A[15:0]), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); // ZBBSelect[2] differentiates between min(u) vs max(u) instruction mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult); diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index cb63eb85a..a9a027ab6 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -30,7 +30,7 @@ module zbc import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] A, RevA, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform + input logic [1:0] Funct3, // Indicates operation to perform output logic [P.XLEN-1:0] ZBCResult); // ZBC result logic [P.XLEN-1:0] ClmulResult, RevClmulResult; diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 466167fb3..175e7df08 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -7,7 +7,7 @@ // // Purpose: Branch comparison // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index f8d3e2122..4dbb8ff82 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -7,7 +7,7 @@ // // Purpose: Top level controller module // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -53,16 +53,13 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic [2:0] ALUSelectE, // ALU mux select signal - output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide - output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation output logic SubArithE, // Subtraction or arithmetic shift output logic JumpE, // jump instruction output logic BranchE, // Branch instruction - output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [3:0] ZBBSelectE, // ZBB mux select signal in Execute stage @@ -81,7 +78,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction output logic [1:0] AtomicM, // Atomic (AMO) instruction output logic [2:0] Funct3M, // Instruction's funct3 field - output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid output logic FWriteIntM, // FPU controller writes integer register file @@ -122,6 +118,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FenceXD; // Fence instruction logic CMOD; // Cache management instruction logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$ + logic MemReadE, CSRReadE; // Instruction reads memory, reads a CSR (needed for Hazard unit) + logic MDUE; // MDU (multiply/divide) operatio + logic SCE; // Store Conditional instruction logic CSRWriteD, CSRWriteE; // CSR write logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ @@ -133,14 +132,12 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic unused; logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write - logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction - logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage - logic [3:0] ZBBSelectD; // ZBB Mux Select Signal + logic RegWriteM; // Instruction writes a register (needed for Hazard unit) logic [1:0] CZeroD; logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions @@ -158,7 +155,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [3:0] CMOpD, CMOpE; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero logic IFUPrefetchD; // instruction prefetch logic LSUPrefetchD, LSUPrefetchE; // data prefetch - logic CMOStallD; // Structural hazards from cache management ops logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check) @@ -329,9 +325,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic BSubArithD; // TRUE for BMU ext, clr, andn, orn, xnor logic BALUSrcBD; // BMU alu src select signal - bmuctrl #(P) bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, + bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD, .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, - .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE); + .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE); if (P.ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -357,7 +353,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // tie off unused bit manipulation signals assign BSelectE = 4'b0000; - assign BSelectD = 4'b0000; assign ZBBSelectE = 4'b0000; assign BALUControlE = 3'b0; assign BMUActiveE = 1'b0; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 30848ea6d..12f4204e7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -7,7 +7,7 @@ // // Purpose: Wally Integer Datapath // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -80,7 +80,6 @@ module datapath import cvw::*; #(parameter cvw_t P) ( // Decode stage signals logic [P.XLEN-1:0] R1D, R2D; // Read data from Rs1 (RD1), Rs2 (RD2) logic [P.XLEN-1:0] ImmExtD; // Extended immediate in Decode stage - logic [4:0] RdD; // Destination register in Decode stage // Execute stage signals logic [P.XLEN-1:0] R1E, R2E; // Source operands read from register file logic [P.XLEN-1:0] ImmExtE; // Extended immediate in Execute stage diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 11ab14419..437797859 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -7,7 +7,7 @@ // // Purpose: Produce sign-extended immediates from various formats // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 38d50e3c3..4f9c62cb3 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -87,7 +87,6 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic [2:0] ResultSrcW; // Selects result in Writeback stage logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage logic [2:0] ALUSelectE; // ALU select mux signal - logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding @@ -99,12 +98,10 @@ module ieu import cvw::*; #(parameter cvw_t P) ( // Forwarding signals logic [4:0] Rs1D, Rs2D; - logic [4:0] Rs2E; // Source registers + logic [4:0] Rs2E; // Source registers logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers - logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages - logic MemReadE, CSRReadE; // Load, CSRRead instruction + logic RegWriteW; // Register will be written in Writeback stage logic BranchSignedE; // Branch does signed comparison on operands - logic MDUE; // Multiply/divide instruction logic BMUActiveE; // Bit manipulation instruction being executed logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active @@ -113,12 +110,12 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, + .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, + .Funct3E, .Funct7E, .IntDivE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, - .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, + .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .RdW, .RdE, .RdM); diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv index fcf2f9eef..ac44916d7 100644 --- a/src/ieu/kmu/packer.sv +++ b/src/ieu/kmu/packer.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module packer #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, + input logic [WIDTH/2-1:0] A, B, input logic [2:0] PackSelect, output logic [WIDTH-1:0] PackResult ); diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv index 61173e982..942a3d9a9 100644 --- a/src/ieu/kmu/zbkb.sv +++ b/src/ieu/kmu/zbkb.sv @@ -26,10 +26,11 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module zbkb #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, - input logic [2:0] Funct3, - input logic [2:0] ZBKBSelect, - output logic [WIDTH-1:0] ZBKBResult + input logic [WIDTH-1:0] A, + input logic [WIDTH/2-1:0] B, + input logic [2:0] Funct3, + input logic [2:0] ZBKBSelect, + output logic [WIDTH-1:0] ZBKBResult ); logic [WIDTH-1:0] Brev8Result; // rev8, brev8 @@ -42,8 +43,8 @@ module zbkb #(parameter WIDTH=32) ( for (j=0; j<8; j=j+1) assign Brev8Result[i*8+j] = A[i*8+7-j]; - packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult); - zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult); + packer #(WIDTH) pack(.A(A[WIDTH/2-1:0]), .B(B[WIDTH/2-1:0]), .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult); + zipper #(WIDTH) zipper(.A, .ZipSelect(Funct3[2]), .ZipResult); // ZBKB Result Select Mux mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult); diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv index 18fe9a657..f7937f267 100644 --- a/src/ieu/kmu/zbkx.sv +++ b/src/ieu/kmu/zbkx.sv @@ -31,8 +31,10 @@ module zbkx #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ZBKXResult ); - logic [WIDTH-1:0] xperm4, xperm4lookup; - logic [WIDTH-1:0] xperm8, xperm8lookup; + logic [WIDTH-1:0] xperm4, xperm8; + /* verilator lint_off UNUSEDSIGNAL */ + logic [WIDTH-1:0] xperm4lookup, xperm8lookup; // not all bits are used + /* verilator lint_on UNUSEDSIGNAL */ int i; always_comb begin diff --git a/src/ieu/kmu/zknde64.sv b/src/ieu/kmu/zknde64.sv index 9c2566718..51d997c12 100644 --- a/src/ieu/kmu/zknde64.sv +++ b/src/ieu/kmu/zknde64.sv @@ -48,8 +48,8 @@ module zknde64 import cvw::*; #(parameter cvw_t P) ( aessbox32 sbox(Sbox0In, Sbox0Out); // Substitute bytes of value obtained for tmp2 using Rijndael sbox // Both ZKND and ZKNE support aes64ks1i and aes64ks2 instructions - aes64ks1i aes64ks1i(.round, .rs1(A), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes)); - aes64ks2 aes64ks2(.rs2(B), .rs1(A), .result(aes64ks2Res)); + aes64ks1i aes64ks1i(.round, .rs1(A[63:32]), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes)); + aes64ks2 aes64ks2(.rs2(B), .rs1(A[63:32]), .result(aes64ks2Res)); // Choose among decrypt, encrypt, key schedule 1, key schedule 2 results mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNDEResult); diff --git a/src/ieu/kmu/zknh64.sv b/src/ieu/kmu/zknh64.sv index 923d5ea48..218837ee8 100644 --- a/src/ieu/kmu/zknh64.sv +++ b/src/ieu/kmu/zknh64.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module zknh64 ( - input logic [63:0] A, B, + input logic [63:0] A, input logic [3:0] ZKNHSelect, output logic [63:0] ZKNHResult ); diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 0cb6beaaa..48359d3ca 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -7,7 +7,7 @@ // // Purpose: 3-port register file // -// Documentation: RISC-V System on Chip Design Chapter 4 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 52d87bb1d..8d4da28d9 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index f045533e3..b3f13d010 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -7,7 +7,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -31,7 +31,7 @@ module RASPredictor import cvw::*; #(parameter cvw_t P)( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, + input logic StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic BPReturnWrongD, // Prediction class is wrong input logic ReturnD, input logic ReturnE, CallE, // Instr class diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 146a9c946..470dc649d 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -72,33 +72,26 @@ module bpred import cvw::*; #(parameter cvw_t P) ( logic [1:0] BPDirF; - logic [P.XLEN-1:0] BPBTAF, RASPCF; - logic BPPCWrongE; - logic IClassWrongE; logic BPDirWrongE; + logic [P.XLEN-1:0] BPBTAF, RASPCF; logic BPPCSrcF; - logic [P.XLEN-1:0] BPPCF; - logic [P.XLEN-1:0] PC0NextF; - logic [P.XLEN-1:0] PCCorrectE; - logic [3:0] WrongPredInstrClassD; + logic [P.XLEN-1:0] BPPCF; + logic [P.XLEN-1:0] PC0NextF; + logic [P.XLEN-1:0] PCCorrectE; - logic BTBTargetWrongE; logic RASTargetWrongE; - logic [P.XLEN-1:0] BPBTAD; - - logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; - logic BPBranchF, BPJumpF, BPReturnF, BPCallF; - logic BPBranchD, BPJumpD, BPReturnD, BPCallD; - logic ReturnD, CallD; - logic ReturnE, CallE; - logic BranchM, JumpM, ReturnM, CallM; - logic BranchW, JumpW, ReturnW, CallW; - logic BPReturnWrongD; - logic [P.XLEN-1:0] BPBTAE; - logic BPBTAWrongM; - logic PCSrcM; + logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; + logic BPBranchF, BPJumpF, BPReturnF, BPCallF; + logic BPBranchD, BPJumpD, BPReturnD, BPCallD; + logic ReturnD, CallD; + logic ReturnE, CallE; + logic BranchM, JumpM, ReturnM, CallM; + logic BranchW, JumpW, ReturnW, CallW; + logic BPReturnWrongD; + logic BPBTAWrongM; + logic PCSrcM; // Part 1 branch direction prediction if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor @@ -154,7 +147,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( btb #(P, P.BTB_SIZE) TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, - .BPBTAF, .BPBTAD, .BPBTAE, + .BPBTAF, .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), .BPBTAWrongM, .IClassWrongM, @@ -170,7 +163,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .BPReturnWrongD); // Part 3 RAS - RASPredictor #(P) RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + RASPredictor #(P) RASPredictor(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .BPReturnF, .ReturnD, .ReturnE, .CallE, .BPReturnWrongD, .RASPCF, .PCLinkE); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e9e0b5bfd..acd61df67 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -8,7 +8,7 @@ // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. // It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -36,8 +36,6 @@ module btb import cvw::*; #(parameter cvw_t P, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, input logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages output logic [P.XLEN-1:0] BPBTAF, // BTB's guess at PC - output logic [P.XLEN-1:0] BPBTAD, - output logic [P.XLEN-1:0] BPBTAE, output logic [3:0] BTBIClassF, // BTB's guess at instruction class output logic BPBTAWrongM, // update @@ -52,11 +50,12 @@ module btb import cvw::*; #(parameter cvw_t P, logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex; logic MatchD, MatchE, MatchM, MatchW, MatchX; - logic [P.XLEN+3:0] ForwardBTBPredF; - logic [P.XLEN+3:0] TableBTBPredF; - logic [P.XLEN-1:0] IEUAdrW; - logic [P.XLEN-1:0] PCW; - logic BTBWrongE, BPBTAWrongE; + logic [P.XLEN+3:0] ForwardBTBPredF; + logic [P.XLEN+3:0] TableBTBPredF; + logic [P.XLEN-1:0] IEUAdrW; + logic [P.XLEN-1:0] PCW; + logic [P.XLEN-1:0] BPBTAD, BPBTAE; + logic BPBTAWrongE; logic BTBWrongM; diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index f17156c25..691926484 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -44,7 +44,7 @@ module gshare import cvw::*; #(parameter cvw_t P, input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM, MatchW; + logic MatchD, MatchE, MatchM, MatchW; logic MatchX; logic [1:0] PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF; diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 5a8c65ecf..512dacfd5 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -6,10 +6,6 @@ // Modified: 18 January 2023 // // Purpose: Expand 16-bit compressed instructions to 32 bits -// -// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1) -// RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97 -// *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 6a223c099..7f70e91a3 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -211,7 +211,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // delay the interrupt until the LSU is in a clean state. assign CommittedF = CacheCommittedF | BusCommittedF; - logic IgnoreRequest; + logic IgnoreRequest; // *** unused; RT: is this a bug or delete? assign IgnoreRequest = ITLBMissF | FlushD; // The IROM uses untranslated addresses, so it is not compatible with virtual memory. diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 49e4ddc82..5b82aac76 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -9,7 +9,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/align.sv b/src/lsu/align.sv index c28c1b9cf..25a2c99d7 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -9,7 +9,7 @@ // It is simlar to the IFU's spill module and probably could be merged together with // some effort. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index a6ee53e73..bc8a29471 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -7,7 +7,7 @@ // // Purpose: Performs AMO operations // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -73,7 +73,7 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( 5'b10100: y = cmp ? a : b; // amomax 5'b11000: y = cmp ? a : b; // amominu 5'b11100: y = cmp ? a : b; // amomaxu - default: y = 'x; // undefined; *** could change to b for efficiency + default: y = 'x; // undefined endcase // sign extend output if necessary for w64 diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 704eb4c62..e318260ab 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -7,7 +7,7 @@ // // Purpose: Wrapper for amoalu and lrsc // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 1386db96f..5bd46deb9 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -7,7 +7,7 @@ // // Purpose: tightly integrated memory into the LSU. // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 7c042886a..3634e2322 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -7,7 +7,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 5981035c1..437907e55 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -8,7 +8,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 43176e04b..58339b0a7 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -9,7 +9,7 @@ // HPTW, DMMU, data cache, interface to external bus // Atomic, Endian swap, and subword read/write logic // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -131,7 +131,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [P.LLEN-1:0] DCacheReadDataWordSpillM; // D$ read data logic [P.LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data logic [P.LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data - logic [P.LLEN-1:0] ReadDataWordM; // Read data before subword selection logic [P.LLEN-1:0] ReadDataM; // Final read data logic [P.XLEN-1:0] IHWriteDataM; // IEU or HPTW write data @@ -380,7 +379,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats. assign LSUHBURST = 3'b0; - assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; + assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0; end end else begin: nobus // block: bus, only DTIM assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index a0e1bfc2f..40e3c11c6 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -7,7 +7,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index eec6fe020..4ae097cc3 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -7,7 +7,7 @@ // // Purpose: Masking and muxing for subword writes // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index fc1f95c4e..cbe4070cc 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -7,7 +7,7 @@ // // Purpose: On-chip RAM, external to core // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/div.sv b/src/mdu/div.sv index 2ae35d8f4..66fe5d9d4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index f478ad86f..d47742fa9 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -6,7 +6,7 @@ // // Purpose: Radix-2 restoring integer division step. k steps are used in div // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 8918e5830..b2f0f7514 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -45,12 +45,6 @@ module mdu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] MDUResultM; // result after W truncation logic W64M; // W-type instruction - logic [P.XLEN-1:0] AMDU, BMDU; // Gated inputs to MDU - - // gate data inputs to MDU to only operate when MDU is active. - assign AMDU = ForwardedSrcAE & {P.XLEN{MDUActiveE}}; - assign BMDU = ForwardedSrcBE & {P.XLEN{MDUActiveE}}; - // Multiplier mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM); diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index 65eaefd82..7c3f13a85 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Integer multiplication // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index bf092dbc6..f4de5a7b7 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index d71fef82a..2ef7c25f1 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 32eef1bf6..5952266e5 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -10,7 +10,7 @@ // // Purpose: Hardware Page Table Walker // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -49,7 +49,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( input logic ITLBMissF, input logic DTLBMissM, input logic FlushW, - input logic InstrUpdateDAF, + input logic InstrUpdateDAF, // *** unused; RT, can we delete or is this a bug? input logic DataUpdateDAM, output logic [P.XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs @@ -105,7 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault; logic HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay; logic HPTWAccessFaultDelay; - logic TakeHPTWFault, TakeHPTWFaultDelay; + logic TakeHPTWFault; logic [P.XLEN-1:0] ReadDataNoXM; logic PBMTFaultM; logic HPTWFaultM; @@ -120,9 +120,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; - flopr #(7) HPTWAccesFaultReg(clk, reset, {TakeHPTWFault, HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, + flopr #(6) HPTWAccesFaultReg(clk, reset, {HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault}, - {TakeHPTWFaultDelay, HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay, + {HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay, HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay}); assign TakeHPTWFault = WalkerState != IDLE; @@ -281,7 +281,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back // to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but // rather than physical address of the translated instruction/data. So we must generate the exception. - // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546) flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) @@ -321,7 +320,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay. // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. - assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; + assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; // *** unused - RT, can we delete? assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index ec41773a8..9130dc3d4 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -71,7 +71,6 @@ module mmu import cvw::*; #(parameter cvw_t P, logic PMPStoreAmoAccessFaultM; // Store or AMO access fault from PMP logic DataMisalignedM; // load or store misaligned logic Translate; // Translation occurs when virtual memory is active and DisableTranslation is off - logic TLBHit; // Hit in TLB logic TLBPageFault; // Page fault from TLB logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise @@ -90,14 +89,15 @@ module mmu import cvw::*; #(parameter cvw_t P, .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation, .PTE, .PageTypeWriteVal, - .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, + .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType); end else begin:tlb // just pass address through as physical assign Translate = 1'b0; assign TLBMiss = 1'b0; - assign TLBHit = 1'b1; // *** is this necessary assign TLBPageFault = 1'b0; assign PBMemoryType = 2'b00; + assign UpdateDA = 1'b0; + assign TLBPAdr = '0; end // If translation is occuring, select translated physical address from TLB diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index b1953cb9b..f2a2e984b 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f5245081..71a6b890a 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 30a525744..a97b7ff2e 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 5fbd10caf..7add2162e 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -72,7 +72,6 @@ module tlb import cvw::*; #(parameter cvw_t P, input logic TLBFlush, output logic [P.PA_BITS-1:0] TLBPAdr, output logic TLBMiss, - output logic TLBHit, output logic Translate, output logic TLBPageFault, output logic UpdateDA, @@ -87,6 +86,7 @@ module tlb import cvw::*; #(parameter cvw_t P, logic [11:0] PTEAccessBits; logic [1:0] HitPageType; logic CAMHit; + logic TLBHit; logic SV39Mode; logic Misaligned; logic MegapageMisaligned; @@ -110,12 +110,12 @@ module tlb import cvw::*; #(parameter cvw_t P, assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4 tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, - .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation, .TLBFlush, + .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation, .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, .TLBMiss, .TLBHit, .TLBPageFault, .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType); - tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .TLBHit, .WriteEnables); + tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .Matches, .TLBHit, .WriteEnables); tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS) tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs, .SATP_ASID, .Matches, .HitPageType, .CAMHit); diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index aa569f2dd..06b66efcc 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index f5856ef56..057c8766b 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 83074deb3..9bd3b8148 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -38,7 +38,6 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( input logic ReadAccess, WriteAccess, input logic [3:0] CMOpM, input logic DisableTranslation, - input logic TLBFlush, // Invalidate all TLB entries input logic [11:0] PTEAccessBits, input logic CAMHit, input logic Misaligned, diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 4776b5afb..6700ddcd0 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -31,7 +31,6 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( input logic clk, reset, input logic TLBWrite, - input logic TLBFlush, input logic [TLB_ENTRIES-1:0] Matches, input logic TLBHit, output logic [TLB_ENTRIES-1:0] WriteEnables diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index d615d1370..502d3ef83 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 620f338a1..3b329705d 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 910db3aec..0b3e3994a 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index d8168dac2..6f2d3c2d4 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -28,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module vm64check import cvw::*; #(parameter cvw_t P) ( - input logic [P.SVMODE_BITS-1:0] SATP_MODE, - input logic [P.XLEN-1:0] VAdr, - output logic SV39Mode, - output logic UpperBitsUnequal + input logic [P.SVMODE_BITS-1:0] SATP_MODE, + input logic [P.XLEN-1:0] VAdr, + output logic SV39Mode, + output logic UpperBitsUnequal ); if (P.XLEN == 64) begin diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index af4dd0dd0..b849cd7e6 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -271,6 +271,8 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign FRM_REGW = '0; assign CSRUReadValM = '0; assign IllegalCSRUAccessM = 1'b1; + assign WriteFRMM = 1'b0; + assign WriteFFLAGSM = 1'b0; end if (P.ZICNTR_SUPPORTED) begin:counters diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index e28d6c1a9..e992ee526 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -7,7 +7,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index fafc5c845..b3db38e8a 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 348002e46..58ca290e2 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -11,7 +11,7 @@ // - Disabling portions of the instruction set with bits of the MISA register // - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -45,8 +45,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, output logic [15:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, + /* verilator lint_off UNDRIVEN */ // PMP registers are only used when PMP_ENTRIES > 0 output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], + /* verilator lint_on UNDRIVEN */ output logic WriteMSTATUSM, WriteMSTATUSHM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM, output logic [63:0] MENVCFG_REGW diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 9623aa8b5..ebd468ad6 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 161bf521c..22f34124c 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register (and environment configuration register and others shared across modes) // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -66,7 +66,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = '0; // does not exist when XLEN=64, and accessing will throw an illegal instruction end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 62ac86c8d..eeb364a89 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -6,7 +6,7 @@ // // Purpose: User-Mode Control and Status Registers for Floating Point // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 60828a3f2..6321413d4 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 4d46b7aed..197ab23be 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index f1c5bfd76..f9a38d501 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -6,7 +6,7 @@ // // Purpose: Track privilege mode. Change on traps and returns. // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index ed43571bd..4cab65c34 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 788b39618..247bfe678 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -6,7 +6,7 @@ // // Purpose: Handle Traps: Exceptions and Interrupts // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index df41c9541..84979ddee 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// Documentation: RISC-V System on Chip Design Chapter 6 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index c416f2938..76735aaa6 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -76,7 +76,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( default: PRDATA <= '0; endcase end - always_ff @(posedge PCLK or negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin MSIP <= 1'b0; MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts @@ -85,14 +85,14 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( if (entry == CLINT_MTIMECMP) begin for(i=0;i wwatermarklevel) | wfull; - assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)}; -endmodule - -module TransmitShiftFSM( - input logic PCLK, PRESETn, - input logic TransmitFIFOReadEmpty, ReceivePenultimateFrame, Active0, - output logic TransmitShiftEmpty); - - always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) TransmitShiftEmpty <= 1'b1; - else if (TransmitShiftEmpty) begin - if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1'b1; - else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 1'b0; - end else begin - if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1'b1; - else TransmitShiftEmpty <= 1'b0; - end - -endmodule - -module ReceiveShiftFSM( - input logic PCLK, PRESETn, SCLKenable, - input logic ReceivePenultimateFrame, SampleEdge, SckMode, - output logic ReceiveShiftFull -); - typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} statetype; - statetype ReceiveState, ReceiveNextState; - always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) ReceiveState <= ReceiveShiftNotFullState; - else if (SCLKenable) begin - case (ReceiveState) - ReceiveShiftFullState: ReceiveState <= ReceiveShiftNotFullState; - ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState; - else ReceiveState <= ReceiveShiftNotFullState; - ReceiveShiftDelayState: ReceiveState <= ReceiveShiftFullState; - endcase - end - - assign ReceiveShiftFull = SckMode ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState); -endmodule - diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv new file mode 100644 index 000000000..40c3ca4ff --- /dev/null +++ b/src/uncore/spi_fifo.sv @@ -0,0 +1,51 @@ +module spi_fifo #(parameter M=3, N=8)( // 2^M entries of N bits each + input logic PCLK, wen, ren, PRESETn, + input logic winc, rinc, + input logic [N-1:0] wdata, + input logic [M-1:0] wwatermarklevel, rwatermarklevel, + output logic [N-1:0] rdata, + output logic wfull, rempty, + output logic wwatermark, rwatermark); + + /* Pointer FIFO using design elements from "Simulation and Synthesis Techniques + for Asynchronous FIFO Design" by Clifford E. Cummings. Namely, M bit read and write pointers + are an extra bit larger than address size to determine full/empty conditions. + Watermark comparisons use 2's complement subtraction between the M-1 bit pointers, + which are also used to address memory + */ + + logic [N-1:0] mem[2**M]; + logic [M:0] rptr, wptr; + logic [M:0] rptrnext, wptrnext; + logic [M-1:0] raddr; + logic [M-1:0] waddr; + + assign rdata = mem[raddr]; + always_ff @(posedge PCLK) + if (winc & ~wfull) mem[waddr] <= wdata; + + // write and read are enabled + always_ff @(posedge PCLK) + if (~PRESETn) begin + rptr <= '0; + wptr <= '0; + wfull <= 1'b0; + rempty <= 1'b1; + end else begin + if (wen) begin + wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr); + wptr <= wptrnext; + end + if (ren) begin + rptr <= rptrnext; + rempty <= (wptr == rptrnext); + end + end + + assign raddr = rptr[M-1:0]; + assign rptrnext = rptr + {{(M){1'b0}}, (rinc & ~rempty)}; + assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull; + assign waddr = wptr[M-1:0]; + assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull; + assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)}; +endmodule diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index f93795be5..7b27ef8e7 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not yet implemented // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -94,7 +94,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( logic [7:0] txfifo[15:0]; logic [4:0] rxfifotailunwrapped; logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; - logic [3:0] rxfifoentries, txfifoentries; + logic [3:0] rxfifoentries; logic [3:0] rxbitsexpected, txbitsexpected; // receive data @@ -145,7 +145,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // Register interface (Table 1, note some are read only and some write only) /////////////////////////////////////////// - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin // Table 3 Reset Configuration IER <= 4'b0; FCR <= 8'b0; @@ -222,7 +222,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // the data, so the baud rate is 320x10^6 / (65 x 2^5 x 16) = 9615 Hz, which is // close enough to 9600 baud to stay synchronized over the duration of one character. /////////////////////////////////////////// - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin baudcount <= 1; baudpulse <= 1'b0; @@ -248,7 +248,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive timing and control /////////////////////////////////////////// - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin rxoversampledcnt <= '0; rxstate <= UART_IDLE; @@ -281,7 +281,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive shift register, buffer register, FIFO /////////////////////////////////////////// - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) rxshiftreg <= 10'b0000000001; // initialize so that there is a valid stop bit else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done @@ -297,7 +297,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // ERROR CONDITIONS assign rxparity = ^rxdata; - assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted) + assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full assign rxframingerr = ~rxstopbit; // framing error if no stop bit assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time @@ -363,7 +363,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( assign rxfifohaserr = |(RXerrbit & rxfullbit); // receive buffer register and ready bit - always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) + always_ff @(posedge PCLK) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) if (~PRESETn) rxfifodmaready <= 1'b0; else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1'b1; else if (rxfifoempty) rxfifodmaready <= 1'b0; @@ -383,7 +383,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // transmit timing and control /////////////////////////////////////////// - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin txoversampledcnt <= '0; txstate <= UART_IDLE; @@ -431,7 +431,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( end // registers & FIFO - always_ff @(posedge PCLK, negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin txfifohead <= '0; txfifotail <= '0; txhrfull <= 1'b0; txsrfull <= 1'b0; TXHR <= '0; txsr <= 12'hfff; end else if (~MEMWb & (A == 3'b010) & Din[2]) begin @@ -467,7 +467,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( end end - always_ff @(posedge PCLK, negedge PRESETn) begin + always_ff @(posedge PCLK) begin // special condition to check if the fifo is empty or full. Because the head // pointer indicates where the next write goes and not the location of the // current head, the head and tail pointer being equal imply two different @@ -484,15 +484,11 @@ module uartPC16550D #(parameter UART_PRESCALE) ( HeadPointerLastMove <= 1'b0; end - assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove; - // verilator lint_off WIDTH - assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : - (txfifohead + 16 - txfifotail); - // verilator lint_on WIDTH - assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove; + assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove; + assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove; // transmit buffer ready bit - always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1) + always_ff @(posedge PCLK) // track txrdy for DMA mode (FCR3 = FCR0 = 1) if (~PRESETn) txfifodmaready <= 1'b0; else if (txfifoempty) txfifodmaready <= 1'b1; else if (txfifofull) txfifodmaready <= 1'b0; diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index c3f8bb31c..f7dcf2a60 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index fb7bb8360..39a2be09a 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -75,11 +75,14 @@ module uncore import cvw::*; #(parameter cvw_t P)( logic SDCIntM; logic PCLK, PRESETn, PWRITE, PENABLE; - logic [4:0] PSEL, PREADY; + logic [4:0] PSEL; logic [31:0] PADDR; logic [P.XLEN-1:0] PWDATA; logic [P.XLEN/8-1:0] PSTRB; + /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration + logic [4:0] PREADY; logic [4:0][P.XLEN-1:0] PRDATA; + /* verilator lint_on UNDRIVEN */ logic [P.XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; @@ -106,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)( ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); - end + end else assign {HREADRam, HRESPRam, HREADYRam} = '0; if (P.BOOTROM_SUPPORTED) begin : bootrom rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom)); - end + end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0; // memory-mapped I/O peripherals if (P.CLINT_SUPPORTED == 1) begin : clint diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index c0bae7af0..a8d30919c 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// Documentation: RISC-V System on Chip Design (Figure 4.1) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -115,8 +115,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic SelHPTW; // PMA checker signals + /* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0]; + /* verilator lint_on UNDRIVEN */ // IMem stalls logic IFUStallF; @@ -351,7 +353,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .SetFflagsM, // FPU flags (to privileged unit) .FIntDivResultW); end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low - assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, + assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM, IllegalFPUInstrD, SetFflagsM, FpLoadStoreM, FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0; end diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 4489646fe..9f5e5ee00 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -6,7 +6,7 @@ // // Purpose: System on chip including pipelined processor and uncore memories/peripherals // -// Documentation: RISC-V System on Chip Design (Figure 6.20) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/studies/comparator.sv b/studies/comparator.sv index 01d38181b..1f9877077 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -7,7 +7,7 @@ // // Purpose: Branch comparison // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/studies/ppa/ppa.sv b/studies/ppa/ppa.sv index 5363bb9b6..6c9311e98 100644 --- a/studies/ppa/ppa.sv +++ b/studies/ppa/ppa.sv @@ -693,8 +693,6 @@ module ppa_mux8_128 #(parameter WIDTH = 128) ( assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); endmodule -// *** some way to express data-critical inputs - module ppa_flop #(parameter WIDTH = 8) ( input logic clk, input logic [WIDTH-1:0] d, diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index ed9d56342..752c8322d 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -64,13 +64,13 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) .loglinebytelen(loglinebytelen), .sramlen(sramlen)) copyShadow(.clk, .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]), + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.ram.RAM[index][P.PA_BITS-1-tagstart:0]), .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), // these dirty bit selections would be needed if dirty is moved inside the tag array. //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.ram.RAM[index]), .index(index), .cacheWord(cacheWord), .CacheData(CacheData[way][index][cacheWord]), @@ -97,7 +97,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; /* verilator lint_off WIDTHTRUNC */ - // *** lint error: address trunc warning for shadowram index + // avoid lint error: address trunc warning for shadowram index ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; /* verilator lint_on WIDTHTRUNC */ end diff --git a/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv index 429ff8489..f4ec8523d 100644 --- a/testbench/common/instrTrackerTB.sv +++ b/testbench/common/instrTrackerTB.sv @@ -34,5 +34,5 @@ module instrTrackerTB( instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); instrNameDecTB mdec(InstrM, InstrMName); - instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU + instrNameDecTB wdec(InstrW, InstrWName); endmodule diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index b8a6389cb..967cf672b 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -261,11 +261,11 @@ module loggers import cvw::*; #(parameter cvw_t P, $fwrite(file, "BEGIN %s\n", memfilename); $fwrite(CFIfile, "BEGIN %s\n", memfilename); end - if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin direction = PCSrcM ? "t" : "n"; $fwrite(file, "%h %s\n", dut.core.PCM, direction); end - if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin direction = PCSrcM ? "t" : "n"; $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction); end diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 17def063c..eed068f54 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -496,13 +496,21 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end + readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile); $fclose(memFile); end else - $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); + $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -511,7 +519,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.ram.RAM[ShadowIndex - BaseIndex]; end end end @@ -519,7 +527,7 @@ module testbench; if (P.DTIM_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin - $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM); $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -528,7 +536,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.ram.RAM[ShadowIndex - BaseIndex]; end end end @@ -539,7 +547,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -725,7 +733,7 @@ end $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); $fatal; end - end else begin // for buildroot use the binary instead to load teh reference model. + end else begin // for buildroot use the binary instead to load the reference model. if (!rvviRefInit("")) begin // still have to call with nothing $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); $fatal; @@ -955,7 +963,7 @@ task automatic updateProgramAddrLabelArray; returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex(); end - end + end // if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile); // if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile); diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 990ebfe74..2794240be 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -26,14 +26,18 @@ `include "config.vh" -import cvw::*; -module wallywrapper; + +module wallywrapper import cvw::*;( + input logic clk, + input logic reset_ext, + input logic SPIIn, + input logic SDCIntr +); `include "parameter-defs.vh" - logic clk; - logic reset_ext, reset; + logic reset; logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -50,9 +54,8 @@ module wallywrapper; logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; - logic SPIIn, SPIOut; + logic SPIOut; logic [3:0] SPICS; - logic SDCIntr; logic HREADY; logic HSELEXT;