From 6a905aa2f2d06274a41b15b1f349585a28aa0b06 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 10 Oct 2024 17:14:27 -0500 Subject: [PATCH 001/141] Possible start to resolution on issue #839. --- src/mmu/hptw.sv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 7a0d2c4a6..daed5dde5 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -274,23 +274,23 @@ module hptw import cvw::*; #(parameter cvw_t P) ( IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // First access in SV48 - L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; - L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; - L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - L0_RD: if (DCacheBusStallM) NextWalkerState = L0_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; From fe5f342d2f282c5a307e6bbcb13b3917ed0ee9c3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 12:07:26 -0500 Subject: [PATCH 002/141] Does not work. But there is a bug hiding the IgnoreRequest confusion. --- src/lsu/lsu.sv | 4 ++-- src/mmu/hptw.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index bc8852cf4..a068bf172 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -342,7 +342,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .FetchBuffer, .CacheBusRW(CacheBusRWTemp), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); - assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; + assign DCacheStallM = CacheStall; assign CacheBusRW = CacheBusRWTemp; ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( @@ -386,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign {DCacheStallM, DCacheCommittedM} = '0; end - assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; + assign LSUBusStallM = BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index daed5dde5..ee22e3a70 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -300,7 +300,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); From 7a92d41ef5d2e70524567559385e3a430b4488c0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 14:41:52 -0500 Subject: [PATCH 003/141] Simplified logic around IgnoreRequest and HPTWFaultM. --- src/lsu/lsu.sv | 18 +++++------------- src/mmu/hptw.sv | 7 +++++-- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index a068bf172..51f4d9d6e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -110,7 +110,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic BusStall; // Bus interface busy with multicycle operation logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall @@ -309,8 +308,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) logic FlushDCache; // Suppress d cache flush if there is an ITLB miss. - logic CacheStall; - logic [1:0] CacheBusRWTemp; logic BusCMOZero; logic [3:0] CacheCMOpM; logic BusAtomic; @@ -336,15 +333,12 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .WriteData(LSUWriteDataSpillM), .SelHPTW, - .CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), + .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), - .FetchBuffer, .CacheBusRW(CacheBusRWTemp), + .FetchBuffer, .CacheBusRW(CacheBusRW), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); - assign DCacheStallM = CacheStall; - assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), @@ -353,7 +347,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), - .BusStall, .BusCommitted(BusCommittedM)); + .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM)); mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}), .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}), @@ -369,7 +363,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), - .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); // Mux between the 2 sources of read data, 0: Bus, 1: DTIM if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); @@ -381,12 +375,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; assign DCacheReadDataWordM = '0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = '0; + assign {LSUBusStallM, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; end - - assign LSUBusStallM = BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index ee22e3a70..deb89b285 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -105,6 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic TakeHPTWFault; logic PBMTFaultM; logic HPTWFaultM; + logic ResetPTE; // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; @@ -143,7 +144,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // State flops flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE; - flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache + flopenr #(P.XLEN) PTEReg(clk, ResetPTE, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values // For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table @@ -300,7 +301,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | + ((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. + assign ResetPTE = reset | (WalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); From 37d3db916b6302cef1bd324866d076db316e54b3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 15:31:20 -0500 Subject: [PATCH 004/141] Resolved the HPTW's not taking the PBMT fault on the right cycle by having the fsm branch to fault on any cycle a HPTWFaultM occurs. This of course changes the figure in the book but it really relevant to PBMT. This appeared to work because the HPTW happened to also generate an access fault at the end of the walk and the logic produced both faults. I wrote new test which confirms just the one is generated. --- src/mmu/hptw.sv | 15 ++-- tests/coverage/nonleafpmbtfault.S | 143 ++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+), 5 deletions(-) create mode 100644 tests/coverage/nonleafpmbtfault.S diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index deb89b285..e48bf85dd 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -278,17 +278,20 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; @@ -302,8 +305,10 @@ module hptw import cvw::*; #(parameter cvw_t P) ( endcase // case (WalkerState) assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | - ((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. - assign ResetPTE = reset | (WalkerState == IDLE); + //((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. + (WalkerState != IDLE & HPTWFaultM); + + assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); diff --git a/tests/coverage/nonleafpmbtfault.S b/tests/coverage/nonleafpmbtfault.S new file mode 100644 index 000000000..8a580ce02 --- /dev/null +++ b/tests/coverage/nonleafpmbtfault.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +// a load or store/amo page fault based on the original access type. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t2, 0x1000 + li t0, 0x8000001000 + + lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + li t1, 0x00008067 + add t0, t0, t2 + sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + + fence.I + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + .8byte 0x200044C1 + +.align 12 + .8byte 0x40000040200048C1 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x2000A0CF + .8byte 0x2000A4CF + .8byte 0x2000A8CF + .8byte 0x2000ACCF + + .8byte 0x2000B0CF + .8byte 0x2000B4CF + .8byte 0x2000B8CF + .8byte 0x2000BCCF + + .8byte 0x2000C0CF + .8byte 0x2000C4CF + .8byte 0x2000C8CF + .8byte 0x2000CCCF + + .8byte 0x2000D0CF + .8byte 0x2000D4CF From 4c7eb1d11f4c863753730f36063e7991356ab363 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 15:41:40 -0500 Subject: [PATCH 005/141] Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW. --- src/lsu/atomic.sv | 4 ++-- src/lsu/lsu.sv | 22 +++++++++++----------- src/mmu/hptw.sv | 6 ++---- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 9c37b636c..8ad9159ce 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -39,7 +39,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal - input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation + input logic LSUFlushW, // On FlushM or TLB miss ignore memory operation output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic SquashSCW, // Store conditional failed disable write to GPR output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC @@ -57,7 +57,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( // LRSC unit if (P.ZALRSC_SUPPORTED) begin - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + assign MemReadM = PreLSURWM[1] & ~LSUFlushW; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin assign SquashSCW = 0; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 51f4d9d6e..08e62f9ad 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -110,7 +110,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB + logic LSUBusStallM; // Bus interface busy with multicycle operation masked by HPTWFlushW logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall @@ -145,8 +145,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic DTLBWriteM; // Writes PTE and PageType to DTLB logic LSULoadAccessFaultM; // Load acces fault logic LSUStoreAmoAccessFaultM; // Store access fault - logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle - logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation + logic HPTWFlushW; // HPTW needs to flush operation + logic LSUFlushW; // HPTW or hazard unit flushes operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; @@ -199,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IHAdrM, .HPTWStall, .SelHPTW, - .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, + .HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF ); @@ -214,7 +214,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0; assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; end @@ -273,7 +273,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Pause IEU memory request if TLB miss. After TLB fill, replay request. // Discard memory request on pipeline flush - assign IgnoreRequest = IgnoreRequestTLB | FlushW; + assign LSUFlushW = HPTWFlushW | FlushW; if (P.DTIM_SUPPORTED) begin : dtim logic [P.PA_BITS-1:0] DTIMAdr; @@ -284,7 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DTIMMemRWM = SelDTIM ? LSURWM : 0; dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), - .DTIMAdr, .FlushW(IgnoreRequest), .WriteDataM(LSUWriteDataM), + .DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); end else assign DTIMReadDataWordM = '0; @@ -328,7 +328,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( - .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(IgnoreRequest), + .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), @@ -340,7 +340,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( - .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), + .HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM), @@ -360,7 +360,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; - ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), + ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); @@ -386,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, - .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 1'b0; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index e48bf85dd..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -58,7 +58,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( output logic [1:0] LSUAtomicM, output logic [2:0] LSUFunct3M, output logic [6:0] LSUFunct7M, - output logic IgnoreRequestTLB, + output logic HPTWFlushW, output logic SelHPTW, output logic HPTWStall, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, @@ -304,9 +304,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | - //((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. - (WalkerState != IDLE & HPTWFaultM); + assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; From 1ded4a972fc96efca6f8e12fc01ec1ca905a281e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 16:02:27 -0500 Subject: [PATCH 006/141] This is a better solution. It's closer to the original book HPTW FSM, but is slightly more complex in RTL. Instead it looks at ReadDataM for the PTE for PBMT faults. I was worried this would cause critical path issues but I think it is ok. ReadDataM is used only to created PBMT and this directly controlls the enable to a flop and the state inputs to the FSM. --- sim/questa/wave.do | 741 +++++++++++++++++++++++---------------------- src/mmu/hptw.sv | 13 +- 2 files changed, 378 insertions(+), 376 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index b00abf659..34079f049 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -72,122 +72,122 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} -add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory -add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr -add wave -noupdate -group ifu -group Bpred -divider {class check} -add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} +add wave -noupdate -expand -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory +add wave -noupdate -expand -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr +add wave -noupdate -expand -group ifu -group Bpred -divider {class check} +add wave -noupdate -expand -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -expand -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -210,219 +210,221 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushStage +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWRW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -666,9 +668,10 @@ add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg +add wave -noupdate /testbench/dut/core/priv/priv/trap/CommittedF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 4} {3636 ns} 0} {{Cursor 4} {787447 ns} 1} {{Cursor 3} {710675 ns} 1} {{Cursor 4} {223860 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -683,4 +686,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1130 ns} {1230 ns} +WaveRestoreZoom {3524 ns} {3788 ns} diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 4e9003dc3..2e9829cb1 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -153,7 +153,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign ValidPTE = Valid & ~(Writable & ~Readable); assign ValidLeafPTE = ValidPTE & LeafPTE; assign ValidNonLeafPTE = Valid & ~LeafPTE; - if(P.XLEN == 64) assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); + // assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); // This is delayed one cycle so use ReadDataM instead + // It's ok for critical path because PBMTFaultM is only used to enable registers and as input to the FSM. + if(P.XLEN == 64) assign PBMTFaultM = ReadDataM[0] & ~(ReadDataM[3] | ReadDataM[2] | ReadDataM[1]) & (|ReadDataM[62:61]) & HPTWRW[1] & ~DCacheBusStallM; else assign PBMTFaultM = 1'b0; if(P.SVADU_SUPPORTED) begin : hptwwrites @@ -278,20 +280,17 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; From 5011084d4028df2e2df17916d370caeea4bf656c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 17:02:51 -0500 Subject: [PATCH 007/141] Revert "This is a better solution. It's closer to the original book HPTW FSM," This actually adds to the critical path and it's more complex than I feel comfortable. This reverts commit 1ded4a972fc96efca6f8e12fc01ec1ca905a281e. --- sim/questa/wave.do | 741 ++++++++++++++++++++++----------------------- src/mmu/hptw.sv | 13 +- 2 files changed, 376 insertions(+), 378 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 34079f049..b00abf659 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -72,122 +72,122 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} -add wave -noupdate -expand -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory -add wave -noupdate -expand -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr -add wave -noupdate -expand -group ifu -group Bpred -divider {class check} -add wave -noupdate -expand -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -expand -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} +add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory +add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr +add wave -noupdate -group ifu -group Bpred -divider {class check} +add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory +add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -210,221 +210,219 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushStage -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWRW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -668,10 +666,9 @@ add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg -add wave -noupdate /testbench/dut/core/priv/priv/trap/CommittedF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {3636 ns} 0} {{Cursor 4} {787447 ns} 1} {{Cursor 3} {710675 ns} 1} {{Cursor 4} {223860 ns} 1} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -686,4 +683,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {3524 ns} {3788 ns} +WaveRestoreZoom {1130 ns} {1230 ns} diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 2e9829cb1..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -153,9 +153,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign ValidPTE = Valid & ~(Writable & ~Readable); assign ValidLeafPTE = ValidPTE & LeafPTE; assign ValidNonLeafPTE = Valid & ~LeafPTE; - // assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); // This is delayed one cycle so use ReadDataM instead - // It's ok for critical path because PBMTFaultM is only used to enable registers and as input to the FSM. - if(P.XLEN == 64) assign PBMTFaultM = ReadDataM[0] & ~(ReadDataM[3] | ReadDataM[2] | ReadDataM[1]) & (|ReadDataM[62:61]) & HPTWRW[1] & ~DCacheBusStallM; + if(P.XLEN == 64) assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); else assign PBMTFaultM = 1'b0; if(P.SVADU_SUPPORTED) begin : hptwwrites @@ -280,17 +278,20 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; From 2ef7005ea63af45d54c4016a80c6db4f3ee8dbed Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 13 Oct 2024 15:29:27 -0500 Subject: [PATCH 008/141] Fixed name of test and added to tests.vh --- testbench/tests.vh | 1 + tests/coverage/{nonleafpmbtfault.S => nonleafpbmtfault.S} | 0 2 files changed, 1 insertion(+) rename tests/coverage/{nonleafpmbtfault.S => nonleafpbmtfault.S} (100%) diff --git a/testbench/tests.vh b/testbench/tests.vh index a91aeda15..bef41ef22 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -60,6 +60,7 @@ string coverage64gc[] = '{ "tlbTP", "tlbMisaligned", "hptwAccessFault", + "nonleafpbmtfault", "amoAccessFault", "floatmisc", "ifuCamlineWrite", diff --git a/tests/coverage/nonleafpmbtfault.S b/tests/coverage/nonleafpbmtfault.S similarity index 100% rename from tests/coverage/nonleafpmbtfault.S rename to tests/coverage/nonleafpbmtfault.S From d5649f6f1d650c90824c5039172f1127ce1c3904 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 17:32:38 -0700 Subject: [PATCH 009/141] Limit number of threads if 8 GB of memory --- bin/wally-tool-chain-install.sh | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 53bc01c8b..7d4dd206d 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -112,11 +112,27 @@ if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then exit 1 fi -# Create installation directory -mkdir -p "$RISCV"/logs +# Check available memory +total_mem=$(grep MemTotal < /proc/meminfo | awk '{print $2}') +total_mem_gb=$((total_mem / 1024 / 1024)) + +# Print system information echo "Running as root: $ROOT" echo "Installation path: $RISCV" +echo "Number of cores: $(nproc)" +echo "Total memory: $total_mem_gb GB" +# Reduce number of threads for systems with less than 8 GB of memory +if ((total_mem < 8400000 )) ; then + NUM_THREADS=1 + echo -e "${WARNING_COLOR}Detected less than or equal to 8 GB of memory. Using a single thread for compiling tools. This may take a while.${ENDC}" +fi + +# Print number of threads +echo "Using $NUM_THREADS thread(s) for compilation" + +# Create installation directory +mkdir -p "$RISCV"/logs # Install/update system packages if root. Otherwise, check that packages are already installed. STATUS="system packages" From da35944dceb6d946e63aace798a8da31117fd722 Mon Sep 17 00:00:00 2001 From: Mysterio-Abdullah Date: Sun, 13 Oct 2024 17:41:59 -0700 Subject: [PATCH 010/141] Configuring Zcb --- addins/cvw-arch-verif | 2 +- config/rv32gc/coverage.svh | 3 +++ config/rv64gc/coverage.svh | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 80cdee231..bbcba7864 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc +Subproject commit bbcba78647080dee82e96bc1b8ff9cd9a3cf7fa1 diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 8fe5d6622..3a04643ad 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -11,3 +11,6 @@ `include "RV32Zfh_coverage.svh" `include "RV32Zicond_coverage.svh" `include "RV32Zca_coverage.svh" +`include "RV32Zcb_coverage.svh" +`include "RV32ZcbM_coverage.svh" +`include "RV32ZcbZbb_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index f21eb2b1a..d1bbaedbb 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -16,3 +16,6 @@ // `include "RV64Zicbom_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" +`include "RV64Zcb_coverage.svh" +`include "RV64ZcbM_coverage.svh" +`include "RV64ZcbZbb_coverage.svh" \ No newline at end of file From 1e34a970684fbbd6743d85fa57f89bb4f8d087fa Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:04:26 -0700 Subject: [PATCH 011/141] Temporarily remove matplotlib --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 462898a60..5445ac69f 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,7 +1,7 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -matplotlib>=3.9.0 +#matplotlib>=3.9.0 PyYAML>=5.2 riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git From 3084fa9c371c13eb88b4b0280594d950585322a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:13:42 -0700 Subject: [PATCH 012/141] Temporarily remove PyYAML from requirements.txt --- bin/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 5445ac69f..a983b8ca4 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,8 +1,8 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -#matplotlib>=3.9.0 -PyYAML>=5.2 +# matplotlib>=3.9.0 +# PyYAML>=5.2 riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 From 0f2dae0da11adb456f42367ef52d18ae540a85a7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:19:21 -0700 Subject: [PATCH 013/141] Temporarily remove sphinx from requirements.txt --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index a983b8ca4..b4280bacc 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 -Sphinx>=7.3.7 +# Sphinx>=7.3.7 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 3c88bb9771666f48709951005ad7f7e4c091ebea Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:23:22 -0700 Subject: [PATCH 014/141] Temporarily remove sphinx-rtd-theme from requirements.txt --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index b4280bacc..d1a102d3a 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -10,5 +10,5 @@ riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 # Sphinx>=7.3.7 -sphinx-rtd-theme>=2.0.0 +# sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 8f3d888da5258ab2a2e19838b2315124f5fb8d11 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 16:04:32 -0700 Subject: [PATCH 015/141] Attempt to install riscof only --- bin/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index d1a102d3a..8cfad9c70 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,9 +3,9 @@ lief>=0.14.1 Markdown>=3.6 # matplotlib>=3.9.0 # PyYAML>=5.2 -riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +# riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git -riscv-config>=3.18.3 +# riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 From 5580bf2fb0914dd1537c0314453920594a0cdd57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 16:06:58 -0700 Subject: [PATCH 016/141] Attempt clone and install riscv-isac --- bin/wally-tool-chain-install.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7d4dd206d..3cc774af3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -176,6 +176,12 @@ pip install --upgrade pip && pip install -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" +# Install riscv-isac +cd $RISCV +STATUS="riscv-isac" +git clone https://github.com/riscv-non-isa/riscv-arch-test +cd riscv-arch-test/riscv-isac +pip install . # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then From 826b3775b61db0338094a637333b3c70d10497eb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 21:52:44 -0700 Subject: [PATCH 017/141] Add setuptools to pip --- bin/requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/requirements.txt b/bin/requirements.txt index 8cfad9c70..22afbb775 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -4,6 +4,7 @@ Markdown>=3.6 # matplotlib>=3.9.0 # PyYAML>=5.2 # riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +setuptools riscof @ git+https://github.com/riscv/riscof.git # riscv-config>=3.18.3 riscv-isac>=0.18.0 From 5f28ee5959239829e3f9309d7e44c488b14a0ecf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:22:20 -0700 Subject: [PATCH 018/141] Test forked riscv-arch-test --- bin/requirements.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 22afbb775..f50d507cb 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,15 +1,15 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -# matplotlib>=3.9.0 -# PyYAML>=5.2 -# riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +matplotlib>=3.9.0 +PyYAML>=5.2 +riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac setuptools riscof @ git+https://github.com/riscv/riscof.git -# riscv-config>=3.18.3 +riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 -# Sphinx>=7.3.7 -# sphinx-rtd-theme>=2.0.0 +Sphinx>=7.3.7 +sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 20b157de628597bc141987bc5292e51e92a83e56 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:39:49 -0700 Subject: [PATCH 019/141] Remove manual riscv-isac installation --- bin/wally-tool-chain-install.sh | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3cc774af3..437023fb8 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -171,18 +171,11 @@ source "$RISCV"/riscv-python/bin/activate # activate python virtual environment # Install python packages, including RISCOF (https://github.com/riscv-software-src/riscof.git) # RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. STATUS="python packages" -pip install --upgrade pip && pip install -r "$dir"/requirements.txt +pip install --upgrade pip && pip install --upgrade -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" -# Install riscv-isac -cd $RISCV -STATUS="riscv-isac" -git clone https://github.com/riscv-non-isa/riscv-arch-test -cd riscv-arch-test/riscv-isac -pip install . - # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then # Newer versin of glib required for QEMU. From 1076b9c179d709ff8b904afdf50c0fc5405233ff Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:44:16 -0700 Subject: [PATCH 020/141] Use python 3.11 for rhel 8 --- bin/wally-package-install.sh | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 725d3b201..94631ad6a 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -46,7 +46,12 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then - PYTHON_VERSION=python3.12 + if (( RHEL_VERSION == 8 )); then + PYTHON_VERSION=python3.11 + elif (( RHEL_VERSION >= 9 )); then + PYTHON_VERSION=python3.12 + VERILATOR_PACKAGES+=(perl-doc) # Not availale in rhel8, nice for Verilator + fi PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) @@ -55,10 +60,6 @@ if [ "$FAMILY" == rhel ]; then SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux - # Extra packages not availale in rhel8, nice for Verilator - if (( RHEL_VERSION >= 9 )); then - VERILATOR_PACKAGES+=(perl-doc) - fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then From ab1797753bbe6778bac35f0cdd9bc5fe86f80cf4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:49:30 -0700 Subject: [PATCH 021/141] Revert "Use python 3.11 for rhel 8" This reverts commit d76cda4dd7613583d41a4bc4624a1915f490a583. --- bin/wally-package-install.sh | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 94631ad6a..725d3b201 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -46,12 +46,7 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then - if (( RHEL_VERSION == 8 )); then - PYTHON_VERSION=python3.11 - elif (( RHEL_VERSION >= 9 )); then - PYTHON_VERSION=python3.12 - VERILATOR_PACKAGES+=(perl-doc) # Not availale in rhel8, nice for Verilator - fi + PYTHON_VERSION=python3.12 PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) @@ -60,6 +55,10 @@ if [ "$FAMILY" == rhel ]; then SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux + # Extra packages not availale in rhel8, nice for Verilator + if (( RHEL_VERSION >= 9 )); then + VERILATOR_PACKAGES+=(perl-doc) + fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then From 1cb22fbe8a17be39dc30aeba8595bac4c2555c46 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 20:35:36 -0700 Subject: [PATCH 022/141] Fix duplicate riscv-isac --- bin/requirements.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index f50d507cb..69c22216e 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,13 +3,12 @@ lief>=0.14.1 Markdown>=3.6 matplotlib>=3.9.0 PyYAML>=5.2 -riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac -setuptools riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 -riscv-isac>=0.18.0 +riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac scikit-learn>=1.5.0 scipy>=1.13.0 +setuptools Sphinx>=7.3.7 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 0cb1ac70f64a0f68c8944ccafd318336d7c8ceee Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:01:15 -0700 Subject: [PATCH 023/141] Limit Sphinx version --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 69c22216e..b29b34507 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7 +Sphinx>=7.3.7, ~=7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 48ee8b0a184613fd330740e30e1721ecae2ce2c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:07:06 -0700 Subject: [PATCH 024/141] Fix sphinx version format --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index b29b34507..10466f601 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7, ~=7 # QEMU fails to build with Sphinx 8 +Sphinx>=7.3.7; ~=7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 77eb250ef66effffc81b3016af342b9efd495d76 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:14:12 -0700 Subject: [PATCH 025/141] Fix sphinx version format --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 10466f601..e5701f08e 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7; ~=7 # QEMU fails to build with Sphinx 8 +Sphinx~=7.3.7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From dc98f29ffaa90842a5495d563e53101a5e0329dd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 23:26:51 -0700 Subject: [PATCH 026/141] Add --no-buildroot option to installation script --- bin/wally-tool-chain-install.sh | 44 ++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 437023fb8..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -77,11 +77,17 @@ trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages # Check for clean flag -if [ "$1" == "--clean" ]; then +if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then clean=true shift fi +# Check for clean flag +if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then + no_buidroot=true + shift +fi + # Determine script directory to locate related scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" @@ -391,23 +397,27 @@ fi # Buildroot and Linux testvectors # Buildroot is used to boot a minimal versio of Linux on Wally. # Testvectors are generated using QEMU. -section_header "Installing Buildroot and Creating Linux testvectors" -STATUS="buildroot" -if [ -z "$LD_LIBRARY_PATH" ]; then - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ +if [ ! "$no_buidroot" ]; then + section_header "Installing Buildroot and Creating Linux testvectors" + STATUS="buildroot" + if [ -z "$LD_LIBRARY_PATH" ]; then + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + else + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + fi + cd "$dir"/../linux + if [ ! -e "$RISCV"/buildroot ]; then + make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" + elif [ ! -e "$RISCV"/linux-testvectors ]; then + echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" + make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" + else + echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + fi else - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ -fi -cd "$dir"/../linux -if [ ! -e "$RISCV"/buildroot ]; then - make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" -elif [ ! -e "$RISCV"/linux-testvectors ]; then - echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" - make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" -else - echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + echo -e "${OK_COLOR}Skipping Buildroot and Linux testvectors.${ENDC}" fi From b8d50fd6217ea513ceae970408bb9a390ad18fa3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:42:47 -0700 Subject: [PATCH 027/141] Switch back to standard riscv-arch-test repo --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index e5701f08e..d55bf7eda 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -5,7 +5,7 @@ matplotlib>=3.9.0 PyYAML>=5.2 riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 -riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac +riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac scikit-learn>=1.5.0 scipy>=1.13.0 setuptools From 64069319589e187c83622b5e815b5fe7deb02cf7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:52:52 -0400 Subject: [PATCH 028/141] Test installation regression GitHub action --- .github/workflows/install.yml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 .github/workflows/install.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml new file mode 100644 index 000000000..bb77a0c62 --- /dev/null +++ b/.github/workflows/install.yml @@ -0,0 +1,14 @@ +name: Installation test + +on: [workflow_dispatch] + +jobs: + install: + name: Test installation on Ubuntu 22.04LTS + runs-on: ubuntu-22.04 + + steps: + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install + From 780147dfd6a072da358c319ef01e9418d47e5bb3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:55:13 -0400 Subject: [PATCH 029/141] Update install.yml --- .github/workflows/install.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index bb77a0c62..eb8255234 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -10,5 +10,8 @@ jobs: steps: - uses: actions/checkout@v4 - name: install - run: sudo ./bin/wally-tool-chain-install + run: | + pwd + cd cvw + sudo ./bin/wally-tool-chain-install From 9f38600caceb4f22ff29c227e8534907ca52db95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:56:24 -0400 Subject: [PATCH 030/141] Update install.yml --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index eb8255234..8a48f690a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -12,6 +12,6 @@ jobs: - name: install run: | pwd - cd cvw - sudo ./bin/wally-tool-chain-install + ls + sudo ./bin/wally-tool-chain-install.sh From ac5a469034ac30332f77581f2d91e007ea79e1cd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 00:11:11 -0400 Subject: [PATCH 031/141] Update install.yml --- .github/workflows/install.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 8a48f690a..ca517a7b0 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,6 +9,9 @@ jobs: steps: - uses: actions/checkout@v4 + - run: sudo apt update + - run: sudo apt upgrade -y + - run: sudo apt install -y libunwind-dev - name: install run: | pwd From 9a399e7ef0e25c789449b409999114f3826f2488 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 10:03:15 -0400 Subject: [PATCH 032/141] Update install.yml --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ca517a7b0..e9ecdd0e5 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -12,6 +12,7 @@ jobs: - run: sudo apt update - run: sudo apt upgrade -y - run: sudo apt install -y libunwind-dev + - run: git clone --recurse-submodules -j 4 https://github.com/qemu/qemu - name: install run: | pwd From 8dcdd71830662e703287e01adb86860fda780207 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 10:08:11 -0400 Subject: [PATCH 033/141] Update install.yml --- .github/workflows/install.yml | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e9ecdd0e5..16da4248e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,13 +9,6 @@ jobs: steps: - uses: actions/checkout@v4 - - run: sudo apt update - - run: sudo apt upgrade -y - - run: sudo apt install -y libunwind-dev - - run: git clone --recurse-submodules -j 4 https://github.com/qemu/qemu - name: install - run: | - pwd - ls - sudo ./bin/wally-tool-chain-install.sh + run: sudo ./bin/wally-tool-chain-install.sh From 9fe94b86d2b1ae8a2a1ab93ceec1b3c3356500a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:12:05 -0400 Subject: [PATCH 034/141] Update install.yml --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 16da4248e..d07636bfa 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,6 +8,7 @@ jobs: runs-on: ubuntu-22.04 steps: + - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From 0029483139d0da88640493fb103d18827729ac23 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:45:34 -0400 Subject: [PATCH 035/141] Update install.yml --- .github/workflows/install.yml | 37 ++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d07636bfa..b8a29a9b4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,7 +9,38 @@ jobs: steps: - run: df -h - - uses: actions/checkout@v4 - - name: install - run: sudo ./bin/wally-tool-chain-install.sh + - run: | + sudo rm -rf /usr/local/lib/android + df -h + - run: | + sudo rm -rf /usr/share/dotnet + df -h + - run: | + sudo rm -rf /opt/ghc + df -h + - run: | + sudo rm -rf /opt/hostedtoolcache/CodeQL + df -h + - run: | + sudo docker image prune --all --force + df -h + - run: | + sudo apt-get purge -y \ + '^llvm-.*' \ + 'php.*' \ + '^mongodb-.*' \ + '^mysql-.*' \ + azure-cli \ + google-cloud-cli \ + google-chrome-stable \ + firefox \ + powershell \ + microsoft-edge-stable \ + mono-devel + sudo apt-get autoremove -y + sudo apt-get clean + df -h + #- uses: actions/checkout@v4 + #- name: install + # run: sudo ./bin/wally-tool-chain-install.sh From 319982a65c10ae222a535a5dc87f7df40b227c86 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:52:43 -0400 Subject: [PATCH 036/141] Update install.yml --- .github/workflows/install.yml | 37 +++++++++++++---------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b8a29a9b4..b3cc2b6f4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,23 +8,13 @@ jobs: runs-on: ubuntu-22.04 steps: - - run: df -h - - run: | - sudo rm -rf /usr/local/lib/android - df -h - - run: | - sudo rm -rf /usr/share/dotnet - df -h - - run: | - sudo rm -rf /opt/ghc - df -h - - run: | - sudo rm -rf /opt/hostedtoolcache/CodeQL - df -h - - run: | - sudo docker image prune --all --force - df -h - - run: | + - name: Free up storage + run: | + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null + sudo docker image prune --all --force &> /dev/null sudo apt-get purge -y \ '^llvm-.*' \ 'php.*' \ @@ -36,11 +26,12 @@ jobs: firefox \ powershell \ microsoft-edge-stable \ - mono-devel - sudo apt-get autoremove -y - sudo apt-get clean + mono-devel \ + &> /dev/null + sudo apt-get autoremove -y &> /dev/null + sudo apt-get clean &> /dev/null df -h - #- uses: actions/checkout@v4 - #- name: install - # run: sudo ./bin/wally-tool-chain-install.sh + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install.sh From 5717089c0219a1eaae6c94c6fa7faf805bbbf96c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 10:00:28 -0400 Subject: [PATCH 037/141] Create rocky.yml --- .github/workflows/rocky.yml | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/rocky.yml diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml new file mode 100644 index 000000000..85ab33eff --- /dev/null +++ b/.github/workflows/rocky.yml @@ -0,0 +1,38 @@ +name: Installation test + +on: [workflow_dispatch] + +jobs: + install: + name: Test installation on Rocky 9 + runs-on: ubuntu-latest + container: rockylinux:8 + + steps: + - name: Free up storage + run: | + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null + sudo docker image prune --all --force &> /dev/null + sudo apt-get purge -y \ + '^llvm-.*' \ + 'php.*' \ + '^mongodb-.*' \ + '^mysql-.*' \ + azure-cli \ + google-cloud-cli \ + google-chrome-stable \ + firefox \ + powershell \ + microsoft-edge-stable \ + mono-devel \ + &> /dev/null + sudo apt-get autoremove -y &> /dev/null + sudo apt-get clean &> /dev/null + df -h + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install.sh + From a111541da596457723096111da54b6e5309b52bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 10:37:41 -0400 Subject: [PATCH 038/141] Update rocky.yml --- .github/workflows/rocky.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 85ab33eff..9c4097aae 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -7,6 +7,9 @@ jobs: name: Test installation on Rocky 9 runs-on: ubuntu-latest container: rockylinux:8 + defaults: + run: + shell: bash steps: - name: Free up storage From 81e3b5024211cb025782bfa63c38c720cb93a3c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 20:27:22 -0400 Subject: [PATCH 039/141] Update rocky.yml --- .github/workflows/rocky.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 9c4097aae..2a828667b 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -12,6 +12,9 @@ jobs: shell: bash steps: + - run: pwd + - run: ls + - run: df -h - name: Free up storage run: | sudo rm -rf /usr/local/lib/android &> /dev/null From e9d1c501eba24899bb3dee738caa9a76319c1372 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 20:30:23 -0400 Subject: [PATCH 040/141] Update rocky.yml --- .github/workflows/rocky.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 2a828667b..72772f357 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -17,11 +17,11 @@ jobs: - run: df -h - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null - sudo docker image prune --all --force &> /dev/null + sudo rm -rf /usr/local/lib/android + sudo rm -rf /usr/share/dotnet + sudo rm -rf /opt/ghc + sudo rm -rf /opt/hostedtoolcache/CodeQL + sudo docker image prune --all --force sudo apt-get purge -y \ '^llvm-.*' \ 'php.*' \ @@ -35,7 +35,7 @@ jobs: microsoft-edge-stable \ mono-devel \ &> /dev/null - sudo apt-get autoremove -y &> /dev/null + sudo apt-get autoremove -y sudo apt-get clean &> /dev/null df -h - uses: actions/checkout@v4 From 9e9e30112752fdbbc61f5a88484e9ace1139785e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:42:24 -0400 Subject: [PATCH 041/141] Update rocky.yml --- .github/workflows/rocky.yml | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 72772f357..7a4bca157 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -12,32 +12,15 @@ jobs: shell: bash steps: - - run: pwd - - run: ls - run: df -h - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android - sudo rm -rf /usr/share/dotnet - sudo rm -rf /opt/ghc - sudo rm -rf /opt/hostedtoolcache/CodeQL - sudo docker image prune --all --force - sudo apt-get purge -y \ - '^llvm-.*' \ - 'php.*' \ - '^mongodb-.*' \ - '^mysql-.*' \ - azure-cli \ - google-cloud-cli \ - google-chrome-stable \ - firefox \ - powershell \ - microsoft-edge-stable \ - mono-devel \ - &> /dev/null - sudo apt-get autoremove -y - sudo apt-get clean &> /dev/null - df -h + rm -rf /usr/local/lib/android + rm -rf /usr/share/dotnet + rm -rf /opt/ghc + rm -rf /opt/hostedtoolcache/CodeQL + docker image prune --all --&> /dev/null + - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From fb40f0477223d0320c9bb16391ece97b57b57b83 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:50:46 -0400 Subject: [PATCH 042/141] Update rocky.yml --- .github/workflows/rocky.yml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 7a4bca157..f9a5450e9 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -13,14 +13,6 @@ jobs: steps: - run: df -h - - name: Free up storage - run: | - rm -rf /usr/local/lib/android - rm -rf /usr/share/dotnet - rm -rf /opt/ghc - rm -rf /opt/hostedtoolcache/CodeQL - docker image prune --all --&> /dev/null - - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From 2e31836e69495f03bc590d94b15882a9b131c344 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:53:05 -0400 Subject: [PATCH 043/141] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index f9a5450e9..a99c13521 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -15,5 +15,5 @@ jobs: - run: df -h - uses: actions/checkout@v4 - name: install - run: sudo ./bin/wally-tool-chain-install.sh + run: ./bin/wally-tool-chain-install.sh From e01c70a9d4a7ab3f5e50a5ffca9e39d45eb8a1e7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:54:55 -0400 Subject: [PATCH 044/141] Update rocky.yml --- .github/workflows/rocky.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index a99c13521..b405864d9 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -13,6 +13,7 @@ jobs: steps: - run: df -h + - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From 19244c9bd708f89351dabf31445a72877f9b4e54 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 08:52:54 -0400 Subject: [PATCH 045/141] Update rocky.yml --- .github/workflows/rocky.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index b405864d9..32f02f000 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -6,13 +6,15 @@ jobs: install: name: Test installation on Rocky 9 runs-on: ubuntu-latest - container: rockylinux:8 defaults: run: shell: bash steps: - run: df -h + - name: free up storage + run: sudo rm -rf /usr/local/lib/android + - run: docker run rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From 653aaa80f4ca823768cef8d5457337ad31d4d915 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 08:59:34 -0400 Subject: [PATCH 046/141] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 32f02f000..ba33a14e3 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -14,7 +14,7 @@ jobs: - run: df -h - name: free up storage run: sudo rm -rf /usr/local/lib/android - - run: docker run rockylinux:8 + - run: docker start -ia rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From b9ff0c18b0136b43624bab1df5374c161f1be0b6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 09:36:44 -0400 Subject: [PATCH 047/141] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index ba33a14e3..be64697c0 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -14,7 +14,7 @@ jobs: - run: df -h - name: free up storage run: sudo rm -rf /usr/local/lib/android - - run: docker start -ia rockylinux:8 + - run: docker run -ia rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From f208b11b51600551e82fb73a19dbc077f4d6789a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 16:51:46 -0500 Subject: [PATCH 048/141] Update hptwAccessFault to generate additional hptw access faults during ifu fetches. --- tests/coverage/hptwAccessFault.S | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index 7c1bc3be1..e1a2ea49c 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -48,7 +48,32 @@ main: lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault add t0, t0, t2 - sw t1, 0(t0) + sw t1, 0(t0) + + j jumppoint + +jumppoint: +.align 6 # aligns to cache line size + sw t1, 0(t0) + sw t1, 4(t0) + sw t1, 8(t0) + sw t1, 12(t0) + sw t1, 16(t0) + sw t1, 20(t0) + sw t1, 24(t0) + sw t1, 28(t0) + sw t1, 32(t0) + sw t1, 36(t0) + sw t1, 40(t0) + sw t1, 44(t0) + sw t1, 48(t0) + sw t1, 52(t0) # this one causes a concurrent I$ miss with HPTW access exception (store access exception) + sw t1, 56(t0) + lw t3, 0(t0) + lw t3, 4(t0) + lw t3, 8(t0) + lw t3, 12(t0) + lw t3, 16(t0) fence.I From 816e54f4510cd5256970dd0e310dda2692e55f72 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 21:29:02 -0500 Subject: [PATCH 049/141] Revert "Revmoed file from fpga zbbl which should not have been added." This reverts commit d6944cdaa46aeacfa095a2da1926d0974efb369e. --- fpga/zsbl/bios.S | 102 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 fpga/zsbl/bios.S diff --git a/fpga/zsbl/bios.S b/fpga/zsbl/bios.S new file mode 100644 index 000000000..a7283b38d --- /dev/null +++ b/fpga/zsbl/bios.S @@ -0,0 +1,102 @@ +#include "system.h" + +PERIOD = (SYSTEMCLOCK / 2) + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, (EXT_MEM_END - 8) + + li a0, 0x00000000 + li a1, EXT_MEM_BASE + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hart ID to a0 + li a1, FDT_ADDRESS # This is the device tree address + la a2, end_of_bios + li t0, EXT_MEM_BASE # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + From 86ec7f609b1ae9d3f0c6323f34cc9d54f0deef4a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:06:38 -0500 Subject: [PATCH 050/141] Updated FPGA readme. --- fpga/README.md | 71 +++++++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 32 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index dfa27479e..fbe9876cc 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,46 +1,53 @@ -The FPGA currently only targets the VCU118 board. +Wally supports the following boards -* Build Process +ArtyA7 +vcu108 +vcu118 + +* Quick Start + +** build FPGA cd generator -make +make -* Description +example +make vcu108 -The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4, -axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks -and builds wally. fpga/src/fpgaTop.v is the top level which instanciates -wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic -analyzer) which provides the current instruction PCM, instrM, etc along with -a large number of debuging signals. +** Make flash card image +ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. +Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). +cd $WALLY/linux/sd-card +This following script requires root. +./flash-sd.sh -b -d -* Programming the flash card -You'll need to write the linux image to the flash card. Use the convert2bin.py -script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt -file from QEMU's preload to generate the binary. Then to copy - sudo dd if=ram.bin of=. +example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc +./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc -* Loading the FPGA +Wait until the the script completes then remove the car. -After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's -gui and open the WallyFPGA.xpr project file. Open the hardware manager under -program and debug. Open target and then program with the bit file. +** FPGA setup -* Test Run +For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card. -Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide -status of the reset and ddr4 calibration. LED 7 should always be lit. -LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once -wally begins running. +For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards. -Next the bootloader program will copy the flash card into the DDR4 memory. -When this done the lower 5 LEDs will blink 5 times and then try to boot -the program loaded in the DDR4 memory at physical address 0x8000_0000. +Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch. +The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the +VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. -* Connecting uart -You'll need to connect both usb cables. The first connects the FPGA programer -while the connect connects UART. UART is configured to use 57600 baud with -no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should -let you view the com port. +cd $WALLY/fpga/generator +vivado & +open the design in the current directory WallyFPGA.xpr. + +Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. + +** Connect to UART + +In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. + +screen /dev/ttyUSB1 115200 + +Swap out the USB1 for USB0 or USB1 as needed. From cdc0ecc87c2c0a03bd005f00f93c23a5d40799a8 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:08:09 -0500 Subject: [PATCH 051/141] FPGA readme now in markdown. --- fpga/README.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index fbe9876cc..3651661f0 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -4,9 +4,9 @@ ArtyA7 vcu108 vcu118 -* Quick Start +# Quick Start -** build FPGA +## build FPGA cd generator make @@ -14,7 +14,7 @@ make example make vcu108 -** Make flash card image +## Make flash card image ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). cd $WALLY/linux/sd-card @@ -26,7 +26,7 @@ example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash Wait until the the script completes then remove the car. -** FPGA setup +## FPGA setup For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card. @@ -43,7 +43,7 @@ open the design in the current directory WallyFPGA.xpr. Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. -** Connect to UART +## Connect to UART In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. From fed88f6b175a0ee537f69651655c4950a6368cac Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:10:28 -0500 Subject: [PATCH 052/141] Better formatting for readme. --- fpga/README.md | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index 3651661f0..236bc7ddb 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,28 +1,32 @@ Wally supports the following boards -ArtyA7 -vcu108 -vcu118 +1. ArtyA7 +2. vcu108 +3. vcu118 (Do not recommend.) # Quick Start ## build FPGA -cd generator -make +`cd generator +make ` example -make vcu108 +`make vcu108` ## Make flash card image ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). -cd $WALLY/linux/sd-card + +`cd $WALLY/linux/sd-card` + This following script requires root. -./flash-sd.sh -b -d + +`./flash-sd.sh -b -d ` example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc -./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc + +`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc` Wait until the the script completes then remove the car. @@ -36,8 +40,8 @@ Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. -cd $WALLY/fpga/generator -vivado & +`cd $WALLY/fpga/generator +vivado &` open the design in the current directory WallyFPGA.xpr. @@ -47,7 +51,7 @@ Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. -screen /dev/ttyUSB1 115200 +`screen /dev/ttyUSB1 115200` Swap out the USB1 for USB0 or USB1 as needed. From d4fc3245b0e4d4421d65c6f04a94a91853bd4dad Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 15 Oct 2024 10:11:12 -0500 Subject: [PATCH 053/141] Removed ahbsdc submodule since it is no longer used. Updated old submodules pointing to ross144 to rosethompson repos. --- .gitmodules | 7 ++----- addins/ahbsdc | 1 - fpga/generator/wally.tcl | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) delete mode 160000 addins/ahbsdc diff --git a/.gitmodules b/.gitmodules index b066104f7..eed0bb58f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,14 +20,11 @@ branch = dev [submodule "addins/branch-predictor-simulator"] path = addins/branch-predictor-simulator - url = https://github.com/ross144/branch-predictor-simulator -[submodule "addins/ahbsdc"] - path = addins/ahbsdc - url = https://github.com/JacobPease/ahbsdc.git + url = https://github.com/rosethompson/branch-predictor-simulator [submodule "addins/verilog-ethernet"] sparseCheckout = true path = addins/verilog-ethernet - url = https://github.com/ross144/verilog-ethernet.git + url = https://github.com/rosethompson/verilog-ethernet.git [submodule "cvw-arch-verif"] path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/addins/ahbsdc b/addins/ahbsdc deleted file mode 160000 index 33418c8dc..000000000 --- a/addins/ahbsdc +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3 diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5151b0e77..3ca0c3360 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -47,7 +47,7 @@ if {$board=="ArtyA7"} { # read in all other rtl add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] +set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset] # define top level From 8fb1673ab321f251d797a14306e097b25d40d826 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 15 Oct 2024 10:27:53 -0500 Subject: [PATCH 054/141] Updated email address authorship for my files. --- bin/CModelBTBAccuracy.sh | 2 +- bin/CModelBranchAccuracy.sh | 2 +- bin/SeparateBranch.sh | 2 +- bin/extractFunctionRadix.sh | 2 +- bin/parseHPMC.py | 2 +- bin/wally-tool-chain-install.sh | 2 +- fpga/rvvidaemon/rvvidaemon.c | 2 +- fpga/src/fpgaTop.sv | 2 +- fpga/src/fpgaTopArtyA7.sv | 2 +- fpga/src/wallypipelinedsocwrapper.sv | 2 +- src/cache/cache.sv | 2 +- src/cache/cacheLRU.sv | 2 +- src/cache/cachefsm.sv | 2 +- src/cache/cacheway.sv | 2 +- src/cache/subcachelineread.sv | 2 +- src/ebu/ahbcacheinterface.sv | 2 +- src/ebu/ahbinterface.sv | 2 +- src/ebu/buscachefsm.sv | 2 +- src/ebu/busfsm.sv | 2 +- src/ebu/controllerinput.sv | 2 +- src/ebu/ebu.sv | 2 +- src/ebu/ebufsmarb.sv | 2 +- src/generic/arrs.sv | 2 +- src/generic/binencoder.sv | 2 +- src/generic/mem/ram1p1rwbe.sv | 2 +- src/generic/mem/ram1p1rwe.sv | 2 +- src/generic/mem/ram2p1r1wbe.sv | 2 +- src/generic/onehotdecoder.sv | 2 +- src/ifu/bpred/RASPredictor.sv | 2 +- src/ifu/bpred/bpred.sv | 2 +- src/ifu/bpred/btb.sv | 2 +- src/ifu/bpred/gshare.sv | 2 +- src/ifu/bpred/gsharebasic.sv | 2 +- src/ifu/bpred/icpred.sv | 2 +- src/ifu/bpred/localaheadbp.sv | 2 +- src/ifu/bpred/localbpbasic.sv | 2 +- src/ifu/bpred/localrepairbp.sv | 2 +- src/ifu/bpred/satCounter2.sv | 2 +- src/ifu/bpred/twoBitPredictor.sv | 2 +- src/ifu/irom.sv | 2 +- src/ifu/spill.sv | 2 +- src/lsu/align.sv | 2 +- src/lsu/atomic.sv | 2 +- src/lsu/dtim.sv | 2 +- src/lsu/lsu.sv | 2 +- src/rvvi/csrindextoaddr.sv | 2 +- src/rvvi/packetizer.sv | 2 +- src/rvvi/priorityaomux.sv | 2 +- src/rvvi/regchangedetect.sv | 2 +- src/rvvi/rvvisynth.sv | 2 +- src/rvvi/triggergen.sv | 2 +- testbench/common/DCacheFlushFSM.sv | 2 +- testbench/common/functionName.sv | 2 +- testbench/common/loggers.sv | 2 +- testbench/common/rvvitbwrapper.sv | 2 +- testbench/common/watchdog.sv | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S | 2 +- 60 files changed, 60 insertions(+), 60 deletions(-) diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 20a65bf98..504edf439 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 23 October 2023 ## Modified: ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 5e0e7bc01..039e38a8b 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index 87648589f..27e0b1962 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index a0480f855..c9446a3b5 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -4,7 +4,7 @@ ## extractFunctionRadix.sh ## ## Written: Rose Thompson -## email: ross1728@gmail.com +## email: rose@rosethompson.net ## Created: March 1, 2021 ## Modified: March 10, 2021 ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 4408f2211..c0137916f 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ########################################### -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 20 September 2023 ## Modified: ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..d27e2a392 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -2,7 +2,7 @@ ########################################### ## Tool chain install script. ## -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 1932038ad..3ac9c6f43 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvi daemon // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 31 May 2024 // Modified: 31 May 2024 // diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 0ecce067b..2bf6aee5e 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index cb350e08a..07c66ff95 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index a1e907913..db382ade1 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // wallypipelinedsocwrapper.sv // -// Written: Rose Thompson ross1728@gmail.com 16 June 2023 +// Written: Rose Thompson rose@rosethompson.net 16 June 2023 // Modified: // // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4c89d08cc..5855afb03 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cache.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 79b277a03..7f1904bbd 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheLRU.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 20 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 28cdc7440..1a39ad17a 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cachefsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 25 August 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index fb9d39f41..addf1a019 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheway // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 2c340c092..262992b52 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // subcachelineread.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 4 February 2022 // Modified: 20 January 2023 // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 572e824bb..f3fc676b0 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbcacheinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 821633f71..5e5406c1f 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 9461bd5c5..f81bfa67a 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 9080dbb83..fbd6fe3f6 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 1c4c360ec..9f644e1d3 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // controllerinput.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 31, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 8242d27e6..642eb6de4 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // abhmulticontroller // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 2e7b345f2..853acd09b 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ebufsmarb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2023 // Modified: 23 January 2023 // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index c0d314dd5..9fa09f4b6 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // arrs.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: November 12, 2021 // // Purpose: resets are typically asynchronous but need to be synchronized to diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 83b245485..558eb759a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // binencoder.sv // -// Written: ross1728@gmail.com November 14, 2022 +// Written: rose@rosethompson.net November 14, 2022 // // Purpose: one-hot to binary encoding. // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index d17262d22..9151a35d2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -2,7 +2,7 @@ // ram1p1r2be.sv // 1 port sram with byte enables // -// Written: ross1728@gmail.com +// Written: rose@rosethompson.net // Created: 3 May 2021 // Modified: 20 January 2023 // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index cdca14e38..84effae19 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -2,7 +2,7 @@ // ram1p1rwe.sv // 1 port sram. // -// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com) +// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net) // Created: 04 April 2023 // // Purpose: ram1p1wre, but without byte-enable. Used for icache data. diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 196aa0875..95840c2cc 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -2,7 +2,7 @@ // ram2p1r1wbe.sv // 2 port sram. // -// Written: ross1728@gmail.com May 3, 2021 +// Written: rose@rosethompson.net May 3, 2021 // Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 9b25feb65..91873c8e8 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // onehotdecoder.sv // -// Written: ross1728@gmail.com July 09, 2021 +// Written: rose@rosethompson.net July 09, 2021 // Modified: // // Purpose: Bin to one hot decoder. Power of 2 only. diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index d72f0e0d8..3bef28881 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 15 February 2021 // Modified: 25 January 2023 // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8d6a55d75..8b8793f27 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // bpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 12 February 2021 // Modified: 19 January 2023 // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e0ee0aaf4..6c6ace763 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: February 15, 2021 // Modified: 24 January 2023 // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 057993536..46702e6b1 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -2,7 +2,7 @@ // gshare.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) // Modified: 20 February 2023 diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index a0563d809..3f88494fe 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -2,7 +2,7 @@ // gsharebasic.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. // Modified: 20 February 2023 diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 01ebaca01..0b1992210 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // icpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: February 26, 2023 // Modified: February 26, 2023 // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index a2c7bda5a..e3d6ef8ed 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -2,7 +2,7 @@ // localaheadbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: local history branch predictor with ahead pipelining and SRAM memories. diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index b5634ef8a..5b2334a3d 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -2,7 +2,7 @@ // localbpbasic // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: Local history branch predictor. Basic implementation without any repair and flop memories. diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 5bb614d7f..e15c77f3c 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -2,7 +2,7 @@ // localrepairbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 15 April 2023 // // Purpose: Local history branch predictor with speculation and repair using CBH. diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index f59cef82b..90cdf4f58 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -2,7 +2,7 @@ // satCounter2.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 13, 2021 // Modified: // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 52a04d6e4..2277f8b9b 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -2,7 +2,7 @@ // twoBitPredictor.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 14, 2021 // Modified: // diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index ebebfbe4a..f85b60a5d 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // irom.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index c3c518913..f073398f3 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 28 January 2022 // Modified: 19 January 2023 // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index db37f4a66..f1e2e1892 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 26 October 2023 // Modified: 26 October 2023 // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 8ad9159ce..cd87d70ac 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // atomic.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 31 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 3fb6c81f6..f6530edc8 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // dtim.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 08e62f9ad..a1dd85d98 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -1,7 +1,7 @@ ///////////////////////////////////////////////////////////////////////////////////////////////////////// // lsu.sv // -// Written: David_Harris@hmc.edu, ross1728@gmail.com +// Written: David_Harris@hmc.edu, rose@rosethompson.net // Created: 9 January 2021 // Modified: 11 January 2023 // diff --git a/src/rvvi/csrindextoaddr.sv b/src/rvvi/csrindextoaddr.sv index 0a843f491..4612dd4ee 100644 --- a/src/rvvi/csrindextoaddr.sv +++ b/src/rvvi/csrindextoaddr.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // csrindextoaddr.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 77c58f467..29a58d383 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // packetizer.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 21 May 2024 // Modified: 21 May 2024 // diff --git a/src/rvvi/priorityaomux.sv b/src/rvvi/priorityaomux.sv index d542c946f..7b119a81f 100644 --- a/src/rvvi/priorityaomux.sv +++ b/src/rvvi/priorityaomux.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // priorityaomux.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/regchangedetect.sv b/src/rvvi/regchangedetect.sv index 8becf867d..31d4ea1ec 100644 --- a/src/rvvi/regchangedetect.sv +++ b/src/rvvi/regchangedetect.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // regchangedetect.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index aa1c55aef..3e8170c93 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvisynth.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2024 // Modified: 23 January 2024 // diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv index 0a4269024..a4e74de91 100644 --- a/src/rvvi/triggergen.sv +++ b/src/rvvi/triggergen.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // triggergen.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: June 26, 2024 // Modified: June 26, 2024 // diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index cde584af2..5764ce26b 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // DCacheFlushFSM.sv // -// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com +// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index eac58f40a..5a14c84a4 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // functionName.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // // Purpose: decode name of function // diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index a9edb7892..6b026257a 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Log branch instructions, log instruction fetches, diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv index bd964d40d..f9c1f316c 100644 --- a/testbench/common/rvvitbwrapper.sv +++ b/testbench/common/rvvitbwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 24 July 2024 // // Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench. diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 9dbf6fa8b..f4b02a2e3 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // watchdog.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Detects if the processor is stuck and halts the simulation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S index 2edd1fc55..f3e3846f3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S index ceb3c3603..2df8c246f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index 31b11874b..e0c724aec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S index 97c3946eb..0e615a943 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 // From 58018ceff6921dc2fdaa7dc982a4862a043db012 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:14:24 -0700 Subject: [PATCH 055/141] More rocky testing --- .github/workflows/{rocky.yml => rockyInstall.yml} | 6 +++--- .github/workflows/rockytest.yml | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) rename .github/workflows/{rocky.yml => rockyInstall.yml} (91%) create mode 100644 .github/workflows/rockytest.yml diff --git a/.github/workflows/rocky.yml b/.github/workflows/rockyInstall.yml similarity index 91% rename from .github/workflows/rocky.yml rename to .github/workflows/rockyInstall.yml index be64697c0..e01ea855f 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rockyInstall.yml @@ -1,4 +1,4 @@ -name: Installation test +name: Rocky installation test on: [workflow_dispatch] @@ -7,7 +7,7 @@ jobs: name: Test installation on Rocky 9 runs-on: ubuntu-latest defaults: - run: + run: shell: bash steps: @@ -19,4 +19,4 @@ jobs: - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh - + diff --git a/.github/workflows/rockytest.yml b/.github/workflows/rockytest.yml new file mode 100644 index 000000000..03fda22ae --- /dev/null +++ b/.github/workflows/rockytest.yml @@ -0,0 +1,15 @@ +name: Rocky Linux 8 Workflow + +on: [workflow_dispatch] + +jobs: + build: + runs-on: ubuntu-latest + steps: + - name: parent os + run: cat /etc/os-release + - name: docker os + uses: docker://rockylinux:8 + with: + entrypoint: /bin/bash + args: cat /etc/os-release \ No newline at end of file From 06f909f9bf457c30426b453fd0740d1e60645efb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:22:53 -0700 Subject: [PATCH 056/141] New rocky approach --- .github/workflows/rockyInstall.yml | 17 +++++++++-------- .github/workflows/rockytest.yml | 15 --------------- 2 files changed, 9 insertions(+), 23 deletions(-) delete mode 100644 .github/workflows/rockytest.yml diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index e01ea855f..cd4c324ee 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -6,16 +6,17 @@ jobs: install: name: Test installation on Rocky 9 runs-on: ubuntu-latest - defaults: - run: - shell: bash - + container: + image: rockylinux:8 + options: --privileged --mount type=bind, source=/, target=/ steps: - - run: df -h - - name: free up storage - run: sudo rm -rf /usr/local/lib/android - - run: docker run -ia rockylinux:8 + - name: check distro + run: cat /etc/os-release - run: dnf install -y sudo + - name: free up storage + run: | + df -h + sudo rm -rf /usr/local/lib/android - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh diff --git a/.github/workflows/rockytest.yml b/.github/workflows/rockytest.yml deleted file mode 100644 index 03fda22ae..000000000 --- a/.github/workflows/rockytest.yml +++ /dev/null @@ -1,15 +0,0 @@ -name: Rocky Linux 8 Workflow - -on: [workflow_dispatch] - -jobs: - build: - runs-on: ubuntu-latest - steps: - - name: parent os - run: cat /etc/os-release - - name: docker os - uses: docker://rockylinux:8 - with: - entrypoint: /bin/bash - args: cat /etc/os-release \ No newline at end of file From f910564fa4fd950ec84cebc9420d72055471795f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:26:41 -0700 Subject: [PATCH 057/141] Update rocky.yml for Rocky 8 testing --- .github/workflows/rockyInstall.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index cd4c324ee..cd35bd855 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -4,11 +4,11 @@ on: [workflow_dispatch] jobs: install: - name: Test installation on Rocky 9 + name: Test installation on Rocky 8 runs-on: ubuntu-latest container: image: rockylinux:8 - options: --privileged --mount type=bind, source=/, target=/ + options: --privileged --mount type=bind,source=/,target=/ steps: - name: check distro run: cat /etc/os-release From 919fd8c2db2c33c8cc01d2e568c4d6591a57909b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:28:12 -0700 Subject: [PATCH 058/141] Update rocky.yml for Rocky 8 testing --- .github/workflows/rockyInstall.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index cd35bd855..ab3780c4a 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -8,7 +8,7 @@ jobs: runs-on: ubuntu-latest container: image: rockylinux:8 - options: --privileged --mount type=bind,source=/,target=/ + options: --privileged --mount type=bind,source=/,target=/host steps: - name: check distro run: cat /etc/os-release @@ -16,7 +16,7 @@ jobs: - name: free up storage run: | df -h - sudo rm -rf /usr/local/lib/android + sudo rm -rf /host/usr/local/lib/android - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From c0ffc56d3857fc53b0d7c7efb480e7ae81599fef Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:32:43 -0700 Subject: [PATCH 059/141] Save space on rocky --- .github/workflows/rockyInstall.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index ab3780c4a..627ab6bcc 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -17,6 +17,10 @@ jobs: run: | df -h sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/opt/ghc &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + df -h - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From 5811099446104fab2ce0668270fe0a05e98d3857 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:14:57 -0700 Subject: [PATCH 060/141] Test all supported distros --- .github/workflows/install.yml | 37 +++++++++++++++++++++++++----- .github/workflows/rockyInstall.yml | 27 ---------------------- 2 files changed, 31 insertions(+), 33 deletions(-) delete mode 100644 .github/workflows/rockyInstall.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b3cc2b6f4..ac25d884b 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,12 +1,14 @@ -name: Installation test +name: Installation on: [workflow_dispatch] jobs: - install: - name: Test installation on Ubuntu 22.04LTS - runs-on: ubuntu-22.04 - + ubuntu_install: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ubuntu-20.04, ubuntu-22.04, ubuntu-24.04] steps: - name: Free up storage run: | @@ -34,4 +36,27 @@ jobs: - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh - + rhel_family_install: + name: Test installation on ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + matrix: + os: [rockylinux:8, rockylinux:9, almalinux:8, almalinux:9] + steps: + - name: check distro + run: cat /etc/os-release + - run: dnf install -y sudo + - name: free up storage + run: | + df -h + sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/opt/ghc &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + df -h + - uses: actions/checkout@v4 + - name: install + run: ./bin/wally-tool-chain-install.sh diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml deleted file mode 100644 index 627ab6bcc..000000000 --- a/.github/workflows/rockyInstall.yml +++ /dev/null @@ -1,27 +0,0 @@ -name: Rocky installation test - -on: [workflow_dispatch] - -jobs: - install: - name: Test installation on Rocky 8 - runs-on: ubuntu-latest - container: - image: rockylinux:8 - options: --privileged --mount type=bind,source=/,target=/host - steps: - - name: check distro - run: cat /etc/os-release - - run: dnf install -y sudo - - name: free up storage - run: | - df -h - sudo rm -rf /host/usr/local/lib/android - sudo rm -rf /host/usr/share/dotnet &> /dev/null - sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null - df -h - - uses: actions/checkout@v4 - - name: install - run: ./bin/wally-tool-chain-install.sh - From 978c6b3d1477d11fbfa58f366267aededb488eee Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:17:16 -0700 Subject: [PATCH 061/141] Add quotes --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ac25d884b..074b5a408 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,7 +8,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - os: [ubuntu-20.04, ubuntu-22.04, ubuntu-24.04] + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - name: Free up storage run: | @@ -44,7 +44,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host strategy: matrix: - os: [rockylinux:8, rockylinux:9, almalinux:8, almalinux:9] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - name: check distro run: cat /etc/os-release From f0b42abd88a0b22f422f4a90212e60a582b740b1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:22:45 -0700 Subject: [PATCH 062/141] fewer targets --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 074b5a408..1fd07a8ca 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,7 +8,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] + os: ["ubuntu-20.04", "ubuntu-22.04"] steps: - name: Free up storage run: | @@ -44,7 +44,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host strategy: matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] + os: ["rockylinux:8", "almalinux:8"] steps: - name: check distro run: cat /etc/os-release From d7af9bbccbf6d42114d9d4093c1cb562828b06ae Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:33:56 -0700 Subject: [PATCH 063/141] Continue install tests if one fails --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 1fd07a8ca..51940249a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -7,6 +7,7 @@ jobs: name: Test installation on ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: + fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04"] steps: @@ -43,6 +44,7 @@ jobs: image: ${{ matrix.os }} options: --privileged --mount type=bind,source=/,target=/host strategy: + fail-fast: false matrix: os: ["rockylinux:8", "almalinux:8"] steps: From 59b8eacf70691efd8e972beeb63784ead48fb524 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:41:54 -0700 Subject: [PATCH 064/141] Add test.yml --- .github/workflows/test.yml | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 000000000..54b201622 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,38 @@ +name: test + +on: [workflow_dispatch] + +jobs: + ubuntu_install: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: ["ubuntu-20.04", "ubuntu-22.04"] + steps: + - uses: actions/checkout@v4 + - name: check + run: | + pwd + ls + cd cvw + ls + rhel_family_install: + name: Test installation on ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + fail-fast: false + matrix: + os: ["rockylinux:8", "almalinux:8"] + steps: + - uses: actions/checkout@v4 + - name: check + run: | + pwd + ls + cd cvw + ls From 6b582cc24885928a417cd94c84343d502e2b3a95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:43:21 -0700 Subject: [PATCH 065/141] Update test --- .github/workflows/test.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 54b201622..50b85c2e7 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -16,8 +16,8 @@ jobs: run: | pwd ls - cd cvw - ls + source setup.sh + echo $PATH rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -34,5 +34,5 @@ jobs: run: | pwd ls - cd cvw - ls + source setup.sh + echo $PATH From 17b3013f8d366f6385b9c57eb3b4a176d7e5a190 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:44:32 -0700 Subject: [PATCH 066/141] update test --- .github/workflows/test.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 50b85c2e7..0c95356f3 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -16,6 +16,7 @@ jobs: run: | pwd ls + mkdir /opt/riscv source setup.sh echo $PATH rhel_family_install: @@ -34,5 +35,6 @@ jobs: run: | pwd ls + mkdir /opt/riscv source setup.sh echo $PATH From 479a59e44be676ac3a3b91e19c2835f35881a5a8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:47:38 -0700 Subject: [PATCH 067/141] Run make and regression-wally in installation test --- .github/workflows/install.yml | 12 +++++++++++ .github/workflows/test.yml | 40 ----------------------------------- 2 files changed, 12 insertions(+), 40 deletions(-) delete mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 51940249a..4c2e36afd 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -37,6 +37,12 @@ jobs: - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh + - name: setup + run: source setup.sh + - name: make tests + run: make + - name: regresssion + run: regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -62,3 +68,9 @@ jobs: - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh + - name: setup + run: source setup.sh + - name: make tests + run: make + - name: regresssion + run: regression-wally diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml deleted file mode 100644 index 0c95356f3..000000000 --- a/.github/workflows/test.yml +++ /dev/null @@ -1,40 +0,0 @@ -name: test - -on: [workflow_dispatch] - -jobs: - ubuntu_install: - name: Test installation on ${{ matrix.os }} - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: ["ubuntu-20.04", "ubuntu-22.04"] - steps: - - uses: actions/checkout@v4 - - name: check - run: | - pwd - ls - mkdir /opt/riscv - source setup.sh - echo $PATH - rhel_family_install: - name: Test installation on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "almalinux:8"] - steps: - - uses: actions/checkout@v4 - - name: check - run: | - pwd - ls - mkdir /opt/riscv - source setup.sh - echo $PATH From fab1b6eab99a64424c7b084e0bb840435c372cea Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:08:52 -0700 Subject: [PATCH 068/141] Checkout submodules in install test action --- .github/workflows/install.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4c2e36afd..31018d685 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -35,6 +35,8 @@ jobs: sudo apt-get clean &> /dev/null df -h - uses: actions/checkout@v4 + with: + submodules: recursive - name: install run: sudo ./bin/wally-tool-chain-install.sh - name: setup @@ -54,8 +56,6 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8"] steps: - - name: check distro - run: cat /etc/os-release - run: dnf install -y sudo - name: free up storage run: | @@ -66,6 +66,8 @@ jobs: sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null df -h - uses: actions/checkout@v4 + with: + submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - name: setup From 4b534acde81edab1c330e403e409bf2d51ec0913 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:13:40 -0700 Subject: [PATCH 069/141] add test --- .github/workflows/test.yml | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 000000000..04285aaf3 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,38 @@ +name: List Storage Space +on: [workflow_dispatch] + + +jobs: + storage-space: + runs-on: ubuntu-22 + + steps: + - name: Root + run: | + df -h + cd / + du -h --max-depth=1 / | sort -h + - name: /usr + run: | + cd /usr + du -h --max-depth=1 / | sort -h + - name: /usr/bin + run: | + cd /usr/bin + du -h --max-depth=1 / | sort -h + - name: /usr/local + run: | + cd /usr/local + du -h --max-depth=1 / | sort -h + - name: /usr/share + run: | + cd /usr/share + du -h --max-depth=1 / | sort -h + - name: /opt + run: | + cd /opt + du -h --max-depth=1 / | sort -h + - name: /opt/hostedtoolcache + run: | + cd /opt/hostedtoolcache + du -h --max-depth=1 / | sort -h From f8b078d0d8f1e2b06dc6c236b7d52032b9c23df5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:20:29 -0700 Subject: [PATCH 070/141] install git in redhat docker test --- .github/workflows/install.yml | 2 +- .github/workflows/test.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 31018d685..4f29a6be1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -56,7 +56,7 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8"] steps: - - run: dnf install -y sudo + - run: dnf install -y sudo git - name: free up storage run: | df -h diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 04285aaf3..1a9c1d8d6 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -4,7 +4,7 @@ on: [workflow_dispatch] jobs: storage-space: - runs-on: ubuntu-22 + runs-on: ubuntu-22.04 steps: - name: Root From c8f473b6b71199b40c7f1cbe9d1484d07ae05945 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:22:01 -0700 Subject: [PATCH 071/141] update test --- .github/workflows/test.yml | 42 +++++++++----------------------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 1a9c1d8d6..a4b65cfcb 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -3,36 +3,14 @@ on: [workflow_dispatch] jobs: - storage-space: - runs-on: ubuntu-22.04 - + check-packages: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - name: Root - run: | - df -h - cd / - du -h --max-depth=1 / | sort -h - - name: /usr - run: | - cd /usr - du -h --max-depth=1 / | sort -h - - name: /usr/bin - run: | - cd /usr/bin - du -h --max-depth=1 / | sort -h - - name: /usr/local - run: | - cd /usr/local - du -h --max-depth=1 / | sort -h - - name: /usr/share - run: | - cd /usr/share - du -h --max-depth=1 / | sort -h - - name: /opt - run: | - cd /opt - du -h --max-depth=1 / | sort -h - - name: /opt/hostedtoolcache - run: | - cd /opt/hostedtoolcache - du -h --max-depth=1 / | sort -h + - name: check packages + run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + + From a384f22554c607e59e020139e313baa73777c999 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 22:43:42 -0700 Subject: [PATCH 072/141] Update test.yml --- .github/workflows/test.yml | 99 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 3 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a4b65cfcb..b41c784bf 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -3,14 +3,107 @@ on: [workflow_dispatch] jobs: - check-packages: - name: Test installation on ${{ matrix.os }} + clean-ubuntu: + name: clean ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: + fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: + - run: df -h + - name: remove packages + run: | + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) + for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true + done + sudo apt-get autoremove -y + sudo apt-get clean + - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + - name: remove dirs + run: | + sudo rm -rf /usr/local/lib/android + sudo rm -rf /usr/share/dotnet + sudo rm -rf /usr/share/swift + sudo rm -rf /usr/share/miniconda + sudo rm -rf /usr/share/az* + sudo rm -rf /usr/share/gradle-* + sudo rm -rf /usr/share/sbt + sudo rm -rf /opt/ghc + sudo rm -rf /usr/local/.ghcup + sudo rm -rf /usr/local/share/powershell + sudo rm -rf /usr/local/lib/node_modules + sudo rm -rf /usr/local/julia* + sudo rm -rf /usr/local/share/chromium + sudo rm -rf /usr/local/share/vcpkg + sudo rm -rf /usr/local/games + sudo rm -rf /usr/local/sqlpackage + sudo rm -rf /usr/lib/google-cloud-sdk + sudo rm -rf /usr/lib/jvm + sudo rm -rf /usr/lib/mono + sudo rm -rf /usr/lib/R + sudo rm -rf /usr/lib/postgresql + sudo rm -rf /usr/lib/heroku + sudo rm -rf /usr/lib/llvm* + sudo rm -rf /usr/lib/firefox + sudo rm -rf /opt/hostedtoolcache + sudo docker image prune --all --force + - run: df -h - + clean-rhel: + name: clean ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + fail-fast: false + matrix: + os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] + steps: + - run: df -h + - name: remove packages + run: | + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) + for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true + done + sudo apt-get autoremove -y + sudo apt-get clean + - run: df -h + - name: check packages + run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + - name: remove dirs + run: | + sudo rm -rf host/usr/local/lib/android + sudo rm -rf host/usr/share/dotnet + sudo rm -rf host/usr/share/swift + sudo rm -rf host/usr/share/miniconda + sudo rm -rf host/usr/share/az* + sudo rm -rf host/usr/share/gradle-* + sudo rm -rf host/usr/share/sbt + sudo rm -rf host/opt/ghc + sudo rm -rf host/usr/local/.ghcup + sudo rm -rf host/usr/local/share/powershell + sudo rm -rf host/usr/local/lib/node_modules + sudo rm -rf host/usr/local/julia* + sudo rm -rf host/usr/local/share/chromium + sudo rm -rf host/usr/local/share/vcpkg + sudo rm -rf host/usr/local/games + sudo rm -rf host/usr/local/sqlpackage + sudo rm -rf host/usr/lib/google-cloud-sdk + sudo rm -rf host/usr/lib/jvm + sudo rm -rf host/usr/lib/mono + sudo rm -rf host/usr/lib/R + sudo rm -rf host/usr/lib/postgresql + sudo rm -rf host/usr/lib/heroku + sudo rm -rf host/usr/lib/llvm* + sudo rm -rf host/usr/lib/firefox + sudo rm -rf host/opt/hostedtoolcache + sudo docker image prune --all --force + - run: df -h From 72e1125c632cbdc222d11a96e943cb2eb853504c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 23:51:29 -0700 Subject: [PATCH 073/141] Update test.yml --- .github/workflows/test.yml | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index b41c784bf..315a9a89b 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -59,22 +59,17 @@ jobs: runs-on: ubuntu-latest container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host + options: --privileged --mount type=bind,source=/,target=/host --pid=host strategy: fail-fast: false matrix: os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] steps: + - uses: actions/checkout@v4 - run: df -h - name: remove packages run: | - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) - for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true - done - sudo apt-get autoremove -y - sudo apt-get clean + nsenter -t 1 -m -u -n -i bash .github/cli-space-cleanup.sh - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From a8105f058d3dc90ab5c0e040acaa7bfab1212ad8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:17:07 -0700 Subject: [PATCH 074/141] Create cli-space-cleanup.sh --- .github/cli-space-cleanup.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 .github/cli-space-cleanup.sh diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh new file mode 100644 index 000000000..035fede94 --- /dev/null +++ b/.github/cli-space-cleanup.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) +for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true +done +sudo apt-get autoremove -y +sudo apt-get clean From 82f8a78f1d329913193f30ce0775a3d166f627e5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:20:46 -0700 Subject: [PATCH 075/141] Update test.yml --- .github/workflows/test.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 315a9a89b..13dda37a0 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -65,11 +65,11 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] steps: + - run: dnf install -y sudo git - uses: actions/checkout@v4 - run: df -h - name: remove packages - run: | - nsenter -t 1 -m -u -n -i bash .github/cli-space-cleanup.sh + run: nsenter -t 1 -m -u -n -i bash /__w/cvw/cvw/.github/cli-space-cleanup.sh - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From ca7f95d5d2b4f62f592da96a33008b98d6f852b4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:52:49 -0700 Subject: [PATCH 076/141] make cli-space-cleanup executable --- .github/cli-space-cleanup.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 .github/cli-space-cleanup.sh diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh old mode 100644 new mode 100755 From 22b3a9bfd1c3ba677bc6affd099adedd5cda9cbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:35:13 -0700 Subject: [PATCH 077/141] Update test.yml --- .github/workflows/test.yml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 13dda37a0..567578e2e 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -57,9 +57,12 @@ jobs: clean-rhel: name: clean ${{ matrix.os }} runs-on: ubuntu-latest + defaults: + run: + shell: bash container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: @@ -69,7 +72,10 @@ jobs: - uses: actions/checkout@v4 - run: df -h - name: remove packages - run: nsenter -t 1 -m -u -n -i bash /__w/cvw/cvw/.github/cli-space-cleanup.sh + run: | + cd .github + ls + nsenter -t 1 -m -u -n -i bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From cd0c090658387552d376d7d10ca040f440cd77f5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:59:51 -0700 Subject: [PATCH 078/141] Update cli-space-cleanup.sh --- .github/cli-space-cleanup.sh | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 035fede94..8fd1cfdc8 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -1,5 +1,3 @@ -#!/bin/bash - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) for pack in "${removePacks[@]}"; do echo "REMOVING ${pack}" From db2cfa88caaedc9d4392408d55328479a108b817 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:23:16 -0700 Subject: [PATCH 079/141] Update test.yml --- .github/workflows/test.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 567578e2e..ff414f151 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -75,7 +75,10 @@ jobs: run: | cd .github ls - nsenter -t 1 -m -u -n -i bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + echo "Standard bash" + bash cli-space-cleanup.sh + echo "nsenter bash" + nsenter -t 1 -m -u -n -i /bin/bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From f5dac34fb740f200ef626269d4a07e96536bc5cf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:25:06 -0700 Subject: [PATCH 080/141] Update install test with space saver --- .github/workflows/install.yml | 90 +++++++++++++++++++++++++---------- 1 file changed, 64 insertions(+), 26 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4f29a6be1..36453511f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,30 +9,44 @@ jobs: strategy: fail-fast: false matrix: - os: ["ubuntu-20.04", "ubuntu-22.04"] + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null - sudo docker image prune --all --force &> /dev/null - sudo apt-get purge -y \ - '^llvm-.*' \ - 'php.*' \ - '^mongodb-.*' \ - '^mysql-.*' \ - azure-cli \ - google-cloud-cli \ - google-chrome-stable \ - firefox \ - powershell \ - microsoft-edge-stable \ - mono-devel \ - &> /dev/null + df -h + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) + for pack in "${removePacks[@]}"; do + sudo apt-get purge -y $pack &> /dev/null || true + done sudo apt-get autoremove -y &> /dev/null sudo apt-get clean &> /dev/null + + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /usr/share/swift &> /dev/null + sudo rm -rf /usr/share/miniconda &> /dev/null + sudo rm -rf /usr/share/az* &> /dev/null + sudo rm -rf /usr/share/gradle-* &> /dev/null + sudo rm -rf /usr/share/sbt &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /usr/local/.ghcup &> /dev/null + sudo rm -rf /usr/local/share/powershell &> /dev/null + sudo rm -rf /usr/local/lib/node_modules &> /dev/null + sudo rm -rf /usr/local/julia* &> /dev/null + sudo rm -rf /usr/local/share/chromium &> /dev/null + sudo rm -rf /usr/local/share/vcpkg &> /dev/null + sudo rm -rf /usr/local/games &> /dev/null + sudo rm -rf /usr/local/sqlpackage &> /dev/null + sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null + sudo rm -rf /usr/lib/jvm &> /dev/null + sudo rm -rf /usr/lib/mono &> /dev/null + sudo rm -rf /usr/lib/R &> /dev/null + sudo rm -rf /usr/lib/postgresql &> /dev/null + sudo rm -rf /usr/lib/heroku &> /dev/null + sudo rm -rf /usr/lib/llvm* &> /dev/null + sudo rm -rf /usr/lib/firefox &> /dev/null + sudo rm -rf /opt/hostedtoolcache &> /dev/null + sudo docker image prune --all --force &> /dev/null df -h - uses: actions/checkout@v4 with: @@ -45,6 +59,7 @@ jobs: run: make - name: regresssion run: regression-wally + rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -54,25 +69,48 @@ jobs: strategy: fail-fast: false matrix: - os: ["rockylinux:8", "almalinux:8"] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - run: dnf install -y sudo git - name: free up storage run: | df -h - sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/local/lib/android &> /dev/null sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/usr/share/swift &> /dev/null + sudo rm -rf /host/usr/share/miniconda &> /dev/null + sudo rm -rf /host/usr/share/az* &> /dev/null + sudo rm -rf /host/usr/share/gradle-* &> /dev/null + sudo rm -rf /host/usr/share/sbt &> /dev/null sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + sudo rm -rf /host/usr/local/.ghcup &> /dev/null + sudo rm -rf /host/usr/local/share/powershell &> /dev/null + sudo rm -rf /host/usr/local/lib/node_modules &> /dev/null + sudo rm -rf /host/usr/local/julia* &> /dev/null + sudo rm -rf /host/usr/local/share/chromium &> /dev/null + sudo rm -rf /host/usr/local/share/vcpkg &> /dev/null + sudo rm -rf /host/usr/local/games &> /dev/null + sudo rm -rf /host/usr/local/sqlpackage &> /dev/null + sudo rm -rf /host/usr/lib/google-cloud-sdk &> /dev/null + sudo rm -rf /host/usr/lib/jvm &> /dev/null + sudo rm -rf /host/usr/lib/mono &> /dev/null + sudo rm -rf /host/usr/lib/R &> /dev/null + sudo rm -rf /host/usr/lib/postgresql &> /dev/null + sudo rm -rf /host/usr/lib/heroku &> /dev/null + sudo rm -rf /host/usr/lib/llvm* &> /dev/null + sudo rm -rf /host/usr/lib/firefox &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache &> /dev/null df -h - uses: actions/checkout@v4 with: submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - - name: setup - run: source setup.sh - name: make tests - run: make + run: | + source setup.sh + make - name: regresssion - run: regression-wally + run: | + source setup.sh + regression-wally From bb7888f59a28a4dc62cddd3be08a25388484cf0c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:25:55 -0700 Subject: [PATCH 081/141] Update test.yml --- .github/workflows/test.yml | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index ff414f151..8aa430252 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -73,12 +73,7 @@ jobs: - run: df -h - name: remove packages run: | - cd .github - ls - echo "Standard bash" - bash cli-space-cleanup.sh - echo "nsenter bash" - nsenter -t 1 -m -u -n -i /bin/bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From 482256cb842440fa733ff64e2f15579f08b20baa Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:42:02 -0700 Subject: [PATCH 082/141] New install action --- .github/cli-space-cleanup.sh | 69 ++++++++++++++++++++++++++++++--- .github/workflows/install.yml | 72 +++++------------------------------ .github/workflows/test.yml | 2 +- 3 files changed, 74 insertions(+), 69 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 8fd1cfdc8..5a85eb1d0 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -1,7 +1,66 @@ -removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) +#!/bin/bash +########################################### +## GitHub runner space cleanup +## +## Written: Jordan Carlin, jcarlin@hmc.edu +## Created: 30 June 2024 +## Modified: +## +## Purpose: Remove unnecessary packages/directories from GitHub Actions runner + +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Remove unnecessary packages +removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true + sudo apt-get purge -y $pack &> /dev/null || true done -sudo apt-get autoremove -y -sudo apt-get clean +sudo apt-get autoremove -y &> /dev/null || true +sudo apt-get clean &> /dev/null || true + +# Remove unnecessary directories +sudo rm -rf /usr/local/lib/android &> /dev/null +sudo rm -rf /usr/share/dotnet &> /dev/null +sudo rm -rf /usr/share/swift &> /dev/null +sudo rm -rf /usr/share/miniconda &> /dev/null +sudo rm -rf /usr/share/az* &> /dev/null +sudo rm -rf /usr/share/gradle-* &> /dev/null +sudo rm -rf /usr/share/sbt &> /dev/null +sudo rm -rf /opt/ghc &> /dev/null +sudo rm -rf /usr/local/.ghcup &> /dev/null +sudo rm -rf /usr/local/share/powershell &> /dev/null +sudo rm -rf /usr/local/lib/node_modules &> /dev/null +sudo rm -rf /usr/local/julia* &> /dev/null +sudo rm -rf /usr/local/share/chromium &> /dev/null +sudo rm -rf /usr/local/share/vcpkg &> /dev/null +sudo rm -rf /usr/local/games &> /dev/null +sudo rm -rf /usr/local/sqlpackage &> /dev/null +sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null +sudo rm -rf /usr/lib/jvm &> /dev/null +sudo rm -rf /usr/lib/mono &> /dev/null +sudo rm -rf /usr/lib/R &> /dev/null +sudo rm -rf /usr/lib/postgresql &> /dev/null +sudo rm -rf /usr/lib/heroku &> /dev/null +sudo rm -rf /usr/lib/llvm* &> /dev/null +sudo rm -rf /usr/lib/firefox &> /dev/null +sudo rm -rf /opt/hostedtoolcache &> /dev/null + +# Clean up docker images +sudo docker image prune --all --force &> /dev/null diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 36453511f..221c39f9f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -14,51 +14,21 @@ jobs: - name: Free up storage run: | df -h - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) - for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack &> /dev/null || true - done - sudo apt-get autoremove -y &> /dev/null - sudo apt-get clean &> /dev/null - - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /usr/share/swift &> /dev/null - sudo rm -rf /usr/share/miniconda &> /dev/null - sudo rm -rf /usr/share/az* &> /dev/null - sudo rm -rf /usr/share/gradle-* &> /dev/null - sudo rm -rf /usr/share/sbt &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /usr/local/.ghcup &> /dev/null - sudo rm -rf /usr/local/share/powershell &> /dev/null - sudo rm -rf /usr/local/lib/node_modules &> /dev/null - sudo rm -rf /usr/local/julia* &> /dev/null - sudo rm -rf /usr/local/share/chromium &> /dev/null - sudo rm -rf /usr/local/share/vcpkg &> /dev/null - sudo rm -rf /usr/local/games &> /dev/null - sudo rm -rf /usr/local/sqlpackage &> /dev/null - sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null - sudo rm -rf /usr/lib/jvm &> /dev/null - sudo rm -rf /usr/lib/mono &> /dev/null - sudo rm -rf /usr/lib/R &> /dev/null - sudo rm -rf /usr/lib/postgresql &> /dev/null - sudo rm -rf /usr/lib/heroku &> /dev/null - sudo rm -rf /usr/lib/llvm* &> /dev/null - sudo rm -rf /usr/lib/firefox &> /dev/null - sudo rm -rf /opt/hostedtoolcache &> /dev/null - sudo docker image prune --all --force &> /dev/null + ./github/cli-space-cleanup.sh df -h - uses: actions/checkout@v4 with: submodules: recursive - name: install run: sudo ./bin/wally-tool-chain-install.sh - - name: setup - run: source setup.sh - name: make tests - run: make + run: | + source setup.sh + make - name: regresssion - run: regression-wally + run: | + source setup.sh + regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -72,34 +42,10 @@ jobs: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - run: dnf install -y sudo git - - name: free up storage + - name: Free up storage run: | df -h - sudo rm -rf /host/usr/local/lib/android &> /dev/null - sudo rm -rf /host/usr/share/dotnet &> /dev/null - sudo rm -rf /host/usr/share/swift &> /dev/null - sudo rm -rf /host/usr/share/miniconda &> /dev/null - sudo rm -rf /host/usr/share/az* &> /dev/null - sudo rm -rf /host/usr/share/gradle-* &> /dev/null - sudo rm -rf /host/usr/share/sbt &> /dev/null - sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/usr/local/.ghcup &> /dev/null - sudo rm -rf /host/usr/local/share/powershell &> /dev/null - sudo rm -rf /host/usr/local/lib/node_modules &> /dev/null - sudo rm -rf /host/usr/local/julia* &> /dev/null - sudo rm -rf /host/usr/local/share/chromium &> /dev/null - sudo rm -rf /host/usr/local/share/vcpkg &> /dev/null - sudo rm -rf /host/usr/local/games &> /dev/null - sudo rm -rf /host/usr/local/sqlpackage &> /dev/null - sudo rm -rf /host/usr/lib/google-cloud-sdk &> /dev/null - sudo rm -rf /host/usr/lib/jvm &> /dev/null - sudo rm -rf /host/usr/lib/mono &> /dev/null - sudo rm -rf /host/usr/lib/R &> /dev/null - sudo rm -rf /host/usr/lib/postgresql &> /dev/null - sudo rm -rf /host/usr/lib/heroku &> /dev/null - sudo rm -rf /host/usr/lib/llvm* &> /dev/null - sudo rm -rf /host/usr/lib/firefox &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache &> /dev/null + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - uses: actions/checkout@v4 with: diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 8aa430252..a39d3b1e1 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -73,7 +73,7 @@ jobs: - run: df -h - name: remove packages run: | - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From 9df1a79f10a7892ca6581fe66a1eccb1e929005c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:46:51 -0700 Subject: [PATCH 083/141] Fix installation workflow curl-minimal dependency --- .github/workflows/install.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 221c39f9f..e67b3f28f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,7 +41,10 @@ jobs: matrix: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - - run: dnf install -y sudo git + - name: Install dependencies + run: | + dnf install -y sudo git + dnf remove -y curl-minimal || true - name: Free up storage run: | df -h From de3bac0f59d7c81d80d373d2525780a1cea5f735 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:50:19 -0700 Subject: [PATCH 084/141] Update cli-space-saver --- .github/cli-space-cleanup.sh | 58 +++++++++++++++++------------------ .github/workflows/install.yml | 20 ++++++------ 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 5a85eb1d0..27fb300d8 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -30,37 +30,37 @@ # Remove unnecessary packages removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack &> /dev/null || true + sudo apt-get purge -y $pack || true done -sudo apt-get autoremove -y &> /dev/null || true -sudo apt-get clean &> /dev/null || true +sudo apt-get autoremove -y || true +sudo apt-get clean || true # Remove unnecessary directories -sudo rm -rf /usr/local/lib/android &> /dev/null -sudo rm -rf /usr/share/dotnet &> /dev/null -sudo rm -rf /usr/share/swift &> /dev/null -sudo rm -rf /usr/share/miniconda &> /dev/null -sudo rm -rf /usr/share/az* &> /dev/null -sudo rm -rf /usr/share/gradle-* &> /dev/null -sudo rm -rf /usr/share/sbt &> /dev/null -sudo rm -rf /opt/ghc &> /dev/null -sudo rm -rf /usr/local/.ghcup &> /dev/null -sudo rm -rf /usr/local/share/powershell &> /dev/null -sudo rm -rf /usr/local/lib/node_modules &> /dev/null -sudo rm -rf /usr/local/julia* &> /dev/null -sudo rm -rf /usr/local/share/chromium &> /dev/null -sudo rm -rf /usr/local/share/vcpkg &> /dev/null -sudo rm -rf /usr/local/games &> /dev/null -sudo rm -rf /usr/local/sqlpackage &> /dev/null -sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null -sudo rm -rf /usr/lib/jvm &> /dev/null -sudo rm -rf /usr/lib/mono &> /dev/null -sudo rm -rf /usr/lib/R &> /dev/null -sudo rm -rf /usr/lib/postgresql &> /dev/null -sudo rm -rf /usr/lib/heroku &> /dev/null -sudo rm -rf /usr/lib/llvm* &> /dev/null -sudo rm -rf /usr/lib/firefox &> /dev/null -sudo rm -rf /opt/hostedtoolcache &> /dev/null +sudo rm -rf /usr/local/lib/android +sudo rm -rf /usr/share/dotnet +sudo rm -rf /usr/share/swift +sudo rm -rf /usr/share/miniconda +sudo rm -rf /usr/share/az* +sudo rm -rf /usr/share/gradle-* +sudo rm -rf /usr/share/sbt +sudo rm -rf /opt/ghc +sudo rm -rf /usr/local/.ghcup +sudo rm -rf /usr/local/share/powershell +sudo rm -rf /usr/local/lib/node_modules +sudo rm -rf /usr/local/julia* +sudo rm -rf /usr/local/share/chromium +sudo rm -rf /usr/local/share/vcpkg +sudo rm -rf /usr/local/games +sudo rm -rf /usr/local/sqlpackage +sudo rm -rf /usr/lib/google-cloud-sdk +sudo rm -rf /usr/lib/jvm +sudo rm -rf /usr/lib/mono +sudo rm -rf /usr/lib/R +sudo rm -rf /usr/lib/postgresql +sudo rm -rf /usr/lib/heroku +sudo rm -rf /usr/lib/llvm* +sudo rm -rf /usr/lib/firefox +sudo rm -rf /opt/hostedtoolcache # Clean up docker images -sudo docker image prune --all --force &> /dev/null +sudo docker image prune --all --force diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e67b3f28f..0dd453b13 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -11,14 +11,14 @@ jobs: matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - name: Free up storage - run: | - df -h - ./github/cli-space-cleanup.sh - df -h - uses: actions/checkout@v4 with: submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh - name: make tests @@ -35,7 +35,7 @@ jobs: runs-on: ubuntu-latest container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: @@ -44,15 +44,15 @@ jobs: - name: Install dependencies run: | dnf install -y sudo git - dnf remove -y curl-minimal || true + dnf install curl -y --allowerasing || true + - uses: actions/checkout@v4 + with: + submodules: recursive - name: Free up storage run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - - uses: actions/checkout@v4 - with: - submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - name: make tests From 51cb85045271a05d1aa44188cb3231e5bd89794f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 07:56:03 -0700 Subject: [PATCH 085/141] Update test.yml --- .github/workflows/test.yml | 131 +++++++++++++------------------------ 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a39d3b1e1..1343c6700 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -1,108 +1,69 @@ -name: List Storage Space +name: Test + on: [workflow_dispatch] - jobs: - clean-ubuntu: - name: clean ${{ matrix.os }} + ubuntu_install: + name: Test on ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - run: df -h - - name: remove packages + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage run: | - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) - for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true - done - sudo apt-get autoremove -y - sudo apt-get clean - - run: df -h - - name: check packages - run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr - - name: remove dirs + df -h + ./.github/cli-space-cleanup.sh + df -h + - run: mkdir -p /opt/riscv + - run: sudo apt install -y python3 python3-pip python3-venv + - run: python3 -m venv /opt/riscv + - run: | + source /opt/riscv/bin/activate + pip install --upgrade pip + pip install -r requirements.txt + - name: make tests run: | - sudo rm -rf /usr/local/lib/android - sudo rm -rf /usr/share/dotnet - sudo rm -rf /usr/share/swift - sudo rm -rf /usr/share/miniconda - sudo rm -rf /usr/share/az* - sudo rm -rf /usr/share/gradle-* - sudo rm -rf /usr/share/sbt - sudo rm -rf /opt/ghc - sudo rm -rf /usr/local/.ghcup - sudo rm -rf /usr/local/share/powershell - sudo rm -rf /usr/local/lib/node_modules - sudo rm -rf /usr/local/julia* - sudo rm -rf /usr/local/share/chromium - sudo rm -rf /usr/local/share/vcpkg - sudo rm -rf /usr/local/games - sudo rm -rf /usr/local/sqlpackage - sudo rm -rf /usr/lib/google-cloud-sdk - sudo rm -rf /usr/lib/jvm - sudo rm -rf /usr/lib/mono - sudo rm -rf /usr/lib/R - sudo rm -rf /usr/lib/postgresql - sudo rm -rf /usr/lib/heroku - sudo rm -rf /usr/lib/llvm* - sudo rm -rf /usr/lib/firefox - sudo rm -rf /opt/hostedtoolcache - sudo docker image prune --all --force - - run: df -h + source setup.sh + source /opt/riscv/bin/activate + make || true - clean-rhel: - name: clean ${{ matrix.os }} + + rhel_family_install: + name: Test on ${{ matrix.os }} runs-on: ubuntu-latest - defaults: - run: - shell: bash container: image: ${{ matrix.os }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: - os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - - run: dnf install -y sudo git + - name: Install dependencies + run: | + dnf install -y sudo git + dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - - run: df -h - - name: remove packages + with: + submodules: recursive + - run: dnf install -y python3.12 python3-pip + - run: mkdir -p /opt/riscv + - run: python3.12 -m venv /opt/riscv + - run: | + source /opt/riscv/bin/activate + pip install --upgrade pip + pip install -r requirements.txt + - name: make tests run: | - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" - - run: df -h - - name: check packages - run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr - - name: remove dirs + source setup.sh + source /opt/riscv/bin/activate + make || true + - name: regresssion run: | - sudo rm -rf host/usr/local/lib/android - sudo rm -rf host/usr/share/dotnet - sudo rm -rf host/usr/share/swift - sudo rm -rf host/usr/share/miniconda - sudo rm -rf host/usr/share/az* - sudo rm -rf host/usr/share/gradle-* - sudo rm -rf host/usr/share/sbt - sudo rm -rf host/opt/ghc - sudo rm -rf host/usr/local/.ghcup - sudo rm -rf host/usr/local/share/powershell - sudo rm -rf host/usr/local/lib/node_modules - sudo rm -rf host/usr/local/julia* - sudo rm -rf host/usr/local/share/chromium - sudo rm -rf host/usr/local/share/vcpkg - sudo rm -rf host/usr/local/games - sudo rm -rf host/usr/local/sqlpackage - sudo rm -rf host/usr/lib/google-cloud-sdk - sudo rm -rf host/usr/lib/jvm - sudo rm -rf host/usr/lib/mono - sudo rm -rf host/usr/lib/R - sudo rm -rf host/usr/lib/postgresql - sudo rm -rf host/usr/lib/heroku - sudo rm -rf host/usr/lib/llvm* - sudo rm -rf host/usr/lib/firefox - sudo rm -rf host/opt/hostedtoolcache - sudo docker image prune --all --force - - run: df -h + source setup.sh + regression-wally From 690326d6acedf2a413f030b9d7c43676fc3ec527 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 21:34:55 -0700 Subject: [PATCH 086/141] Update shell --- .github/cli-space-cleanup.sh | 3 +- .github/workflows/install.yml | 4 ++- .github/workflows/test.yml | 64 +++++------------------------------ 3 files changed, 13 insertions(+), 58 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 27fb300d8..0f8de1619 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -30,7 +30,7 @@ # Remove unnecessary packages removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack || true + sudo apt-get purge -y "$pack" || true done sudo apt-get autoremove -y || true sudo apt-get clean || true @@ -58,7 +58,6 @@ sudo rm -rf /usr/lib/mono sudo rm -rf /usr/lib/R sudo rm -rf /usr/lib/postgresql sudo rm -rf /usr/lib/heroku -sudo rm -rf /usr/lib/llvm* sudo rm -rf /usr/lib/firefox sudo rm -rf /opt/hostedtoolcache diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0dd453b13..ec7a0cf34 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,6 +1,8 @@ name: Installation - on: [workflow_dispatch] +defaults: + run: + shell: bash jobs: ubuntu_install: diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 1343c6700..18f9cb34c 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -1,6 +1,8 @@ name: Test - on: [workflow_dispatch] +defaults: + run: + shell: bash jobs: ubuntu_install: @@ -12,58 +14,10 @@ jobs: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - uses: actions/checkout@v4 - with: - submodules: recursive - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - run: mkdir -p /opt/riscv - - run: sudo apt install -y python3 python3-pip python3-venv - - run: python3 -m venv /opt/riscv + # with: + # submodules: recursive - run: | - source /opt/riscv/bin/activate - pip install --upgrade pip - pip install -r requirements.txt - - name: make tests - run: | - source setup.sh - source /opt/riscv/bin/activate - make || true - - - rhel_family_install: - name: Test on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] - steps: - - name: Install dependencies - run: | - dnf install -y sudo git - dnf install curl -y --allowerasing || true - - uses: actions/checkout@v4 - with: - submodules: recursive - - run: dnf install -y python3.12 python3-pip - - run: mkdir -p /opt/riscv - - run: python3.12 -m venv /opt/riscv - - run: | - source /opt/riscv/bin/activate - pip install --upgrade pip - pip install -r requirements.txt - - name: make tests - run: | - source setup.sh - source /opt/riscv/bin/activate - make || true - - name: regresssion - run: | - source setup.sh - regression-wally + df -h + ./.github/cli-space-cleanup.sh + df -h + - run: sudo ./bin/wally-package-install.sh From 60cc2be07fa2b91bd42b3248e1cba93b9ed66814 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 18 Jul 2024 23:36:11 -0700 Subject: [PATCH 087/141] Remove test.yml --- .github/workflows/test.yml | 23 ----------------------- 1 file changed, 23 deletions(-) delete mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml deleted file mode 100644 index 18f9cb34c..000000000 --- a/.github/workflows/test.yml +++ /dev/null @@ -1,23 +0,0 @@ -name: Test -on: [workflow_dispatch] -defaults: - run: - shell: bash - -jobs: - ubuntu_install: - name: Test on ${{ matrix.os }} - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] - steps: - - uses: actions/checkout@v4 - # with: - # submodules: recursive - - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - run: sudo ./bin/wally-package-install.sh From 306e5d4042e9d6a2cbb59c38b092c74d78dbd648 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 19:00:14 -0700 Subject: [PATCH 088/141] Add clean + update checks --- .github/workflows/install.yml | 4 ++-- bin/wally-tool-chain-install.sh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ec7a0cf34..52cb45f95 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -22,7 +22,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh @@ -56,7 +56,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: ./bin/wally-tool-chain-install.sh + run: ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..1905d484c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -72,7 +72,7 @@ logger() { cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) } -set -e # break on error +set -ex # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages From 56c39e764c5bbce17d49ed1fceb1be2e75a7190c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 19:39:21 -0700 Subject: [PATCH 089/141] updates --- bin/wally-tool-chain-install.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 1905d484c..ad83f3f8f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,6 +46,7 @@ ENDC='\033[0m' # Reset to default color ## Helper functions # Error handler error() { + set +x echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." From 2cb5189db817569243274d4ff2cdf22da75fa45e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 20:47:58 -0700 Subject: [PATCH 090/141] no buildroot --- bin/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 16286c60b..a591aaf61 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -421,8 +421,8 @@ elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_fp, coveragesim) else: for sim in sims: - if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one - addTests(tests_buildrootshort, sim) + # if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one + # addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) From 60c92e99c763ceb75d8416dacefef2bbeaac7ff7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 22:50:43 -0700 Subject: [PATCH 091/141] Make all git directories safe in installation action --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 52cb45f95..4b207b9ad 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -50,6 +50,8 @@ jobs: - uses: actions/checkout@v4 with: submodules: recursive + - name: Fix git ownership + run: git config --global --add safe.directory '*' - name: Free up storage run: | df -h From 535ca9535bee4c2d6bdb643230c6bef38fdfb61a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 14:54:21 -0700 Subject: [PATCH 092/141] Manually run wsim --- .github/workflows/install.yml | 74 ++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4b207b9ad..2543d86f9 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -66,4 +66,76 @@ jobs: - name: regresssion run: | source setup.sh - regression-wally + lint-wally + wsim --sim verilator rv32e arch32e + wsim --sim verilator rv32i arch32i + wsim --sim verilator rv32imc arch32i + wsim --sim verilator rv32imc arch32c + wsim --sim verilator rv32imc arch32m + wsim --sim verilator rv32imc wally32periph + wsim --sim verilator rv32gc arch32f + wsim --sim verilator rv32gc arch32d + wsim --sim verilator rv32gc arch32f_fma + wsim --sim verilator rv32gc arch32d_fma + wsim --sim verilator rv32gc arch32f_divsqrt + wsim --sim verilator rv32gc arch32d_divsqrt + wsim --sim verilator rv32gc arch32i + wsim --sim verilator rv32gc arch32priv + wsim --sim verilator rv32gc arch32c + wsim --sim verilator rv32gc arch32m + wsim --sim verilator rv32gc arch32a_amo + wsim --sim verilator rv32gc arch32zifencei + wsim --sim verilator rv32gc arch32zicond + wsim --sim verilator rv32gc arch32zba + wsim --sim verilator rv32gc arch32zbb + wsim --sim verilator rv32gc arch32zbc + wsim --sim verilator rv32gc arch32zbs + wsim --sim verilator rv32gc arch32zfh + wsim --sim verilator rv32gc arch32zfh_fma + wsim --sim verilator rv32gc arch32zfh_divsqrt + wsim --sim verilator rv32gc arch32zfaf + wsim --sim verilator rv32gc arch32zfad + wsim --sim verilator rv32gc wally32a_lrsc + wsim --sim verilator rv32gc wally32priv + wsim --sim verilator rv32gc wally32periph + wsim --sim verilator rv32gc arch32zcb + wsim --sim verilator rv32gc arch32zbkb + wsim --sim verilator rv32gc arch32zbkc + wsim --sim verilator rv32gc arch32zbkx + wsim --sim verilator rv32gc arch32zknd + wsim --sim verilator rv32gc arch32zkne + wsim --sim verilator rv32gc arch32zknh + wsim --sim verilator rv64i arch64i + wsim --sim verilator rv64gc coverage64gc + wsim --sim verilator rv64gc arch64i + wsim --sim verilator rv64gc arch64priv + wsim --sim verilator rv64gc arch64c + wsim --sim verilator rv64gc arch64m + wsim --sim verilator rv64gc arch64zcb + wsim --sim verilator rv64gc arch64zifencei + wsim --sim verilator rv64gc arch64zicond + wsim --sim verilator rv64gc arch64a_amo + wsim --sim verilator rv64gc wally64a_lrsc + wsim --sim verilator rv64gc wally64periph + wsim --sim verilator rv64gc wally64priv + wsim --sim verilator rv64gc arch64zbkb + wsim --sim verilator rv64gc arch64zbkc + wsim --sim verilator rv64gc arch64zbkx + wsim --sim verilator rv64gc arch64zknd + wsim --sim verilator rv64gc arch64zkne + wsim --sim verilator rv64gc arch64zknh + wsim --sim verilator rv64gc arch64zba + wsim --sim verilator rv64gc arch64zbb + wsim --sim verilator rv64gc arch64zbc + wsim --sim verilator rv64gc arch64zbs + wsim --sim verilator rv64gc arch64f + wsim --sim verilator rv64gc arch64d + wsim --sim verilator rv64gc arch64zfh + wsim --sim verilator rv64gc arch64f_fma + wsim --sim verilator rv64gc arch64d_fma + wsim --sim verilator rv64gc arch64zfh_fma + wsim --sim verilator rv64gc arch64f_divsqrt + wsim --sim verilator rv64gc arch64d_divsqrt + wsim --sim verilator rv64gc arch64zfh_divsqrt + wsim --sim verilator rv64gc arch64zfaf + wsim --sim verilator rv64gc arch64zfad From 9b2aa1ae5f9f35bb94eeb4619d6f32059b28b653 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 11:52:37 -0700 Subject: [PATCH 093/141] Only build riscof tests in installation ci --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 2543d86f9..f5854ed72 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -26,7 +26,7 @@ jobs: - name: make tests run: | source setup.sh - make + make riscof - name: regresssion run: | source setup.sh @@ -62,7 +62,7 @@ jobs: - name: make tests run: | source setup.sh - make + make riscof - name: regresssion run: | source setup.sh From dfd27de6963b12c788274ac6e7b8a8de5e296949 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 18:01:39 -0700 Subject: [PATCH 094/141] Update install.yml --- .github/workflows/install.yml | 74 ++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index f5854ed72..cb7ac9002 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,79 @@ jobs: - name: regresssion run: | source setup.sh - regression-wally + lint-wally + wsim --sim verilator rv32e arch32e + wsim --sim verilator rv32i arch32i + wsim --sim verilator rv32imc arch32i + wsim --sim verilator rv32imc arch32c + wsim --sim verilator rv32imc arch32m + wsim --sim verilator rv32imc wally32periph + wsim --sim verilator rv32gc arch32f + wsim --sim verilator rv32gc arch32d + wsim --sim verilator rv32gc arch32f_fma + wsim --sim verilator rv32gc arch32d_fma + wsim --sim verilator rv32gc arch32f_divsqrt + wsim --sim verilator rv32gc arch32d_divsqrt + wsim --sim verilator rv32gc arch32i + wsim --sim verilator rv32gc arch32priv + wsim --sim verilator rv32gc arch32c + wsim --sim verilator rv32gc arch32m + wsim --sim verilator rv32gc arch32a_amo + wsim --sim verilator rv32gc arch32zifencei + wsim --sim verilator rv32gc arch32zicond + wsim --sim verilator rv32gc arch32zba + wsim --sim verilator rv32gc arch32zbb + wsim --sim verilator rv32gc arch32zbc + wsim --sim verilator rv32gc arch32zbs + wsim --sim verilator rv32gc arch32zfh + wsim --sim verilator rv32gc arch32zfh_fma + wsim --sim verilator rv32gc arch32zfh_divsqrt + wsim --sim verilator rv32gc arch32zfaf + wsim --sim verilator rv32gc arch32zfad + wsim --sim verilator rv32gc wally32a_lrsc + wsim --sim verilator rv32gc wally32priv + wsim --sim verilator rv32gc wally32periph + wsim --sim verilator rv32gc arch32zcb + wsim --sim verilator rv32gc arch32zbkb + wsim --sim verilator rv32gc arch32zbkc + wsim --sim verilator rv32gc arch32zbkx + wsim --sim verilator rv32gc arch32zknd + wsim --sim verilator rv32gc arch32zkne + wsim --sim verilator rv32gc arch32zknh + wsim --sim verilator rv64i arch64i + wsim --sim verilator rv64gc coverage64gc + wsim --sim verilator rv64gc arch64i + wsim --sim verilator rv64gc arch64priv + wsim --sim verilator rv64gc arch64c + wsim --sim verilator rv64gc arch64m + wsim --sim verilator rv64gc arch64zcb + wsim --sim verilator rv64gc arch64zifencei + wsim --sim verilator rv64gc arch64zicond + wsim --sim verilator rv64gc arch64a_amo + wsim --sim verilator rv64gc wally64a_lrsc + wsim --sim verilator rv64gc wally64periph + wsim --sim verilator rv64gc wally64priv + wsim --sim verilator rv64gc arch64zbkb + wsim --sim verilator rv64gc arch64zbkc + wsim --sim verilator rv64gc arch64zbkx + wsim --sim verilator rv64gc arch64zknd + wsim --sim verilator rv64gc arch64zkne + wsim --sim verilator rv64gc arch64zknh + wsim --sim verilator rv64gc arch64zba + wsim --sim verilator rv64gc arch64zbb + wsim --sim verilator rv64gc arch64zbc + wsim --sim verilator rv64gc arch64zbs + wsim --sim verilator rv64gc arch64f + wsim --sim verilator rv64gc arch64d + wsim --sim verilator rv64gc arch64zfh + wsim --sim verilator rv64gc arch64f_fma + wsim --sim verilator rv64gc arch64d_fma + wsim --sim verilator rv64gc arch64zfh_fma + wsim --sim verilator rv64gc arch64f_divsqrt + wsim --sim verilator rv64gc arch64d_divsqrt + wsim --sim verilator rv64gc arch64zfh_divsqrt + wsim --sim verilator rv64gc arch64zfaf + wsim --sim verilator rv64gc arch64zfad rhel_family_install: name: Test installation on ${{ matrix.os }} From a9d2fbdedd34a6a35b123df2053c2a0ff46c4a56 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 23:16:35 -0700 Subject: [PATCH 095/141] Use regression-wally in install cli --- .github/workflows/install.yml | 150 +--------------------------------- 1 file changed, 3 insertions(+), 147 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index cb7ac9002..7b07c5636 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,79 +30,7 @@ jobs: - name: regresssion run: | source setup.sh - lint-wally - wsim --sim verilator rv32e arch32e - wsim --sim verilator rv32i arch32i - wsim --sim verilator rv32imc arch32i - wsim --sim verilator rv32imc arch32c - wsim --sim verilator rv32imc arch32m - wsim --sim verilator rv32imc wally32periph - wsim --sim verilator rv32gc arch32f - wsim --sim verilator rv32gc arch32d - wsim --sim verilator rv32gc arch32f_fma - wsim --sim verilator rv32gc arch32d_fma - wsim --sim verilator rv32gc arch32f_divsqrt - wsim --sim verilator rv32gc arch32d_divsqrt - wsim --sim verilator rv32gc arch32i - wsim --sim verilator rv32gc arch32priv - wsim --sim verilator rv32gc arch32c - wsim --sim verilator rv32gc arch32m - wsim --sim verilator rv32gc arch32a_amo - wsim --sim verilator rv32gc arch32zifencei - wsim --sim verilator rv32gc arch32zicond - wsim --sim verilator rv32gc arch32zba - wsim --sim verilator rv32gc arch32zbb - wsim --sim verilator rv32gc arch32zbc - wsim --sim verilator rv32gc arch32zbs - wsim --sim verilator rv32gc arch32zfh - wsim --sim verilator rv32gc arch32zfh_fma - wsim --sim verilator rv32gc arch32zfh_divsqrt - wsim --sim verilator rv32gc arch32zfaf - wsim --sim verilator rv32gc arch32zfad - wsim --sim verilator rv32gc wally32a_lrsc - wsim --sim verilator rv32gc wally32priv - wsim --sim verilator rv32gc wally32periph - wsim --sim verilator rv32gc arch32zcb - wsim --sim verilator rv32gc arch32zbkb - wsim --sim verilator rv32gc arch32zbkc - wsim --sim verilator rv32gc arch32zbkx - wsim --sim verilator rv32gc arch32zknd - wsim --sim verilator rv32gc arch32zkne - wsim --sim verilator rv32gc arch32zknh - wsim --sim verilator rv64i arch64i - wsim --sim verilator rv64gc coverage64gc - wsim --sim verilator rv64gc arch64i - wsim --sim verilator rv64gc arch64priv - wsim --sim verilator rv64gc arch64c - wsim --sim verilator rv64gc arch64m - wsim --sim verilator rv64gc arch64zcb - wsim --sim verilator rv64gc arch64zifencei - wsim --sim verilator rv64gc arch64zicond - wsim --sim verilator rv64gc arch64a_amo - wsim --sim verilator rv64gc wally64a_lrsc - wsim --sim verilator rv64gc wally64periph - wsim --sim verilator rv64gc wally64priv - wsim --sim verilator rv64gc arch64zbkb - wsim --sim verilator rv64gc arch64zbkc - wsim --sim verilator rv64gc arch64zbkx - wsim --sim verilator rv64gc arch64zknd - wsim --sim verilator rv64gc arch64zkne - wsim --sim verilator rv64gc arch64zknh - wsim --sim verilator rv64gc arch64zba - wsim --sim verilator rv64gc arch64zbb - wsim --sim verilator rv64gc arch64zbc - wsim --sim verilator rv64gc arch64zbs - wsim --sim verilator rv64gc arch64f - wsim --sim verilator rv64gc arch64d - wsim --sim verilator rv64gc arch64zfh - wsim --sim verilator rv64gc arch64f_fma - wsim --sim verilator rv64gc arch64d_fma - wsim --sim verilator rv64gc arch64zfh_fma - wsim --sim verilator rv64gc arch64f_divsqrt - wsim --sim verilator rv64gc arch64d_divsqrt - wsim --sim verilator rv64gc arch64zfh_divsqrt - wsim --sim verilator rv64gc arch64zfaf - wsim --sim verilator rv64gc arch64zfad + regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -135,79 +63,7 @@ jobs: run: | source setup.sh make riscof - - name: regresssion + - name: regression run: | source setup.sh - lint-wally - wsim --sim verilator rv32e arch32e - wsim --sim verilator rv32i arch32i - wsim --sim verilator rv32imc arch32i - wsim --sim verilator rv32imc arch32c - wsim --sim verilator rv32imc arch32m - wsim --sim verilator rv32imc wally32periph - wsim --sim verilator rv32gc arch32f - wsim --sim verilator rv32gc arch32d - wsim --sim verilator rv32gc arch32f_fma - wsim --sim verilator rv32gc arch32d_fma - wsim --sim verilator rv32gc arch32f_divsqrt - wsim --sim verilator rv32gc arch32d_divsqrt - wsim --sim verilator rv32gc arch32i - wsim --sim verilator rv32gc arch32priv - wsim --sim verilator rv32gc arch32c - wsim --sim verilator rv32gc arch32m - wsim --sim verilator rv32gc arch32a_amo - wsim --sim verilator rv32gc arch32zifencei - wsim --sim verilator rv32gc arch32zicond - wsim --sim verilator rv32gc arch32zba - wsim --sim verilator rv32gc arch32zbb - wsim --sim verilator rv32gc arch32zbc - wsim --sim verilator rv32gc arch32zbs - wsim --sim verilator rv32gc arch32zfh - wsim --sim verilator rv32gc arch32zfh_fma - wsim --sim verilator rv32gc arch32zfh_divsqrt - wsim --sim verilator rv32gc arch32zfaf - wsim --sim verilator rv32gc arch32zfad - wsim --sim verilator rv32gc wally32a_lrsc - wsim --sim verilator rv32gc wally32priv - wsim --sim verilator rv32gc wally32periph - wsim --sim verilator rv32gc arch32zcb - wsim --sim verilator rv32gc arch32zbkb - wsim --sim verilator rv32gc arch32zbkc - wsim --sim verilator rv32gc arch32zbkx - wsim --sim verilator rv32gc arch32zknd - wsim --sim verilator rv32gc arch32zkne - wsim --sim verilator rv32gc arch32zknh - wsim --sim verilator rv64i arch64i - wsim --sim verilator rv64gc coverage64gc - wsim --sim verilator rv64gc arch64i - wsim --sim verilator rv64gc arch64priv - wsim --sim verilator rv64gc arch64c - wsim --sim verilator rv64gc arch64m - wsim --sim verilator rv64gc arch64zcb - wsim --sim verilator rv64gc arch64zifencei - wsim --sim verilator rv64gc arch64zicond - wsim --sim verilator rv64gc arch64a_amo - wsim --sim verilator rv64gc wally64a_lrsc - wsim --sim verilator rv64gc wally64periph - wsim --sim verilator rv64gc wally64priv - wsim --sim verilator rv64gc arch64zbkb - wsim --sim verilator rv64gc arch64zbkc - wsim --sim verilator rv64gc arch64zbkx - wsim --sim verilator rv64gc arch64zknd - wsim --sim verilator rv64gc arch64zkne - wsim --sim verilator rv64gc arch64zknh - wsim --sim verilator rv64gc arch64zba - wsim --sim verilator rv64gc arch64zbb - wsim --sim verilator rv64gc arch64zbc - wsim --sim verilator rv64gc arch64zbs - wsim --sim verilator rv64gc arch64f - wsim --sim verilator rv64gc arch64d - wsim --sim verilator rv64gc arch64zfh - wsim --sim verilator rv64gc arch64f_fma - wsim --sim verilator rv64gc arch64d_fma - wsim --sim verilator rv64gc arch64zfh_fma - wsim --sim verilator rv64gc arch64f_divsqrt - wsim --sim verilator rv64gc arch64d_divsqrt - wsim --sim verilator rv64gc arch64zfh_divsqrt - wsim --sim verilator rv64gc arch64zfaf - wsim --sim verilator rv64gc arch64zfad + regression-wally From d613a1b2f9ede52c456bcd7cf14470e25773f0d3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 11:16:08 -0700 Subject: [PATCH 096/141] Upload logs --- .github/workflows/install.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 7b07c5636..8d6abfd2f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,6 +31,11 @@ jobs: run: | source setup.sh regression-wally + - uses: actions/upload-artifact@v2 + if: always() + with: + name: regression-logs-${{ matrix.os }} + path: ${{ github.workspace }}/sim/verilator/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -67,3 +72,8 @@ jobs: run: | source setup.sh regression-wally + - uses: actions/upload-artifact@v2 + if: always() + with: + name: regression-logs-${{ matrix.os }} + path: ${{ github.workspace }}/sim/verilator/logs/ From 864fb199f0bea8dcc55dbee256e21f796e55efc0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 14:16:12 -0700 Subject: [PATCH 097/141] Update artifact upload --- .github/workflows/install.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 8d6abfd2f..b422ae762 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,5 +1,5 @@ name: Installation -on: [workflow_dispatch] +on: [workflow_dispatch, push] defaults: run: shell: bash @@ -31,7 +31,7 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ matrix.os }} @@ -48,6 +48,11 @@ jobs: matrix: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: + - name: Unique name for Artifacts + id: prep_artifact_name + run: | + name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - name: Install dependencies run: | dnf install -y sudo git @@ -72,8 +77,8 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 if: always() with: - name: regression-logs-${{ matrix.os }} + name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ From 269399946c639165190aea082c4f9d1b83cf1bd5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 00:19:20 -0700 Subject: [PATCH 098/141] Save installation logs --- .github/workflows/install.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b422ae762..158113b25 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -36,6 +36,11 @@ jobs: with: name: regression-logs-${{ matrix.os }} path: ${{ github.workspace }}/sim/verilator/logs/ + - uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ matrix.os }} + path: /opt/riscv/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -82,3 +87,8 @@ jobs: with: name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ + - uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ env.ARTIFACT_NAME }} + path: /opt/riscv/logs/ From 63b387619d5dd47184320b19d10e116777a4b441 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 02:00:27 -0700 Subject: [PATCH 099/141] Add buildroot to installation test --- .github/workflows/install.yml | 6 +++++- bin/regression-wally | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 158113b25..6b989b7ad 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -27,7 +27,11 @@ jobs: run: | source setup.sh make riscof - - name: regresssion + - name: make buildroot + run: | + source setup.sh + make -C linux + - name: regression run: | source setup.sh regression-wally diff --git a/bin/regression-wally b/bin/regression-wally index a591aaf61..16286c60b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -421,8 +421,8 @@ elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_fp, coveragesim) else: for sim in sims: - # if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one - # addTests(tests_buildrootshort, sim) + if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one + addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) From 84ee1f0b179898a4c9726faf8aa9769a17aaae19 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 15:57:30 -0700 Subject: [PATCH 100/141] Rhel buildroot --- .github/workflows/install.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 6b989b7ad..e97be456e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -82,6 +82,10 @@ jobs: run: | source setup.sh make riscof + - name: make buildroot + run: | + source setup.sh + make -C linux - name: regression run: | source setup.sh From f115ee9e722ef07529f7525e5e4a6c333d46768f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 23:35:11 -0700 Subject: [PATCH 101/141] Run make linux with sudo in installation test --- .github/workflows/install.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e97be456e..56b80f757 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,7 @@ jobs: - name: make buildroot run: | source setup.sh - make -C linux + sudo make -C linux - name: regression run: | source setup.sh @@ -77,7 +77,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make buildroot run: | source setup.sh - make -C linux + sudo make -C linux - name: regression run: | source setup.sh From 50fc27cb454dc1a95f23eecf359f50eef2d66ada Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 12:36:33 -0700 Subject: [PATCH 102/141] Log buildroot test --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 56b80f757..c66187ff2 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux + sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux + sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From a4c585ca56c31bee48ac1a0879f7fa081fe8e288 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 19:51:31 -0700 Subject: [PATCH 103/141] Change number of riscof jobs in installation test action; restore default to 4 --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c66187ff2..b63c57211 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -26,6 +26,7 @@ jobs: - name: make tests run: | source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: make buildroot run: | @@ -81,6 +82,7 @@ jobs: - name: make tests run: | source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: make buildroot run: | From f47fbdcb05b1eaf0c077a9d195e577f0ead532bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 22:41:13 -0700 Subject: [PATCH 104/141] Update install test to preserve variables for buildroot build --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b63c57211..03ed7a82c 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,7 +31,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -87,7 +87,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 04ddfa0bd07b05e81773dcf00a98f6df974f0345 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 11:47:08 -0700 Subject: [PATCH 105/141] Update install test with buildroot changes --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 03ed7a82c..0788e9883 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,7 +31,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -87,7 +87,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 32522fcf3d0cc618885127b58e0b0b49893b5f03 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 12:42:15 -0700 Subject: [PATCH 106/141] Switch test install to use buildroot from install script --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0788e9883..4e7cfdc9e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -23,15 +23,15 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean + - name: check buildroot + run: | + source setup.sh + ls $RISCV/linux-testvectors - name: make tests run: | source setup.sh sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - - name: make buildroot - run: | - source setup.sh - make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From d528eddab5a6fb51d3a9a7928fc7d1c90e7eacc3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 15:21:43 -0700 Subject: [PATCH 107/141] Switch rhel installation test to use install script buildroot --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4e7cfdc9e..b300044f8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -79,15 +79,15 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean + - name: check buildroot + run: | + source setup.sh + ls $RISCV/linux-testvectors - name: make tests run: | source setup.sh sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - - name: make buildroot - run: | - source setup.sh - make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 62157df494b905f212fef660e930fae6e3af42fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 17:26:24 -0700 Subject: [PATCH 108/141] Turn off debugging messages --- bin/wally-tool-chain-install.sh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ad83f3f8f..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,7 +46,6 @@ ENDC='\033[0m' # Reset to default color ## Helper functions # Error handler error() { - set +x echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." @@ -73,7 +72,7 @@ logger() { cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) } -set -ex # break on error +set -e # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages From 5f9e34788a14bd3654e7ec2822f9d69e93046a8d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 7 Aug 2024 22:02:33 -0700 Subject: [PATCH 109/141] Update installation test logging --- .github/workflows/install.yml | 106 +++++++++++++++++++++++++++++----- 1 file changed, 90 insertions(+), 16 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b300044f8..74a9f58b1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -23,10 +23,12 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: check buildroot - run: | - source setup.sh - ls $RISCV/linux-testvectors + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ matrix.os }} + path: /opt/riscv/logs/ - name: make tests run: | source setup.sh @@ -36,16 +38,12 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v4 + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ matrix.os }} path: ${{ github.workspace }}/sim/verilator/logs/ - - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-${{ matrix.os }} - path: /opt/riscv/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -79,10 +77,12 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: check buildroot - run: | - source setup.sh - ls $RISCV/linux-testvectors + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ env.ARTIFACT_NAME }} + path: /opt/riscv/logs/ - name: make tests run: | source setup.sh @@ -92,12 +92,86 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v4 + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ - - uses: actions/upload-artifact@v4 + + + user_install: + name: Test installation with user permissions + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h + - name: install packages with sudo + run: sudo ./bin/wally-package-install.sh + - name: install + run: ./bin/wally-tool-chain-install.sh --clean + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-user-install + path: ~/riscv/logs/ + - name: make tests + run: | + source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini + make riscof + - name: regression + run: | + source setup.sh + regression-wally + - name: Upload regression logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: regression-logs-user-install + path: ${{ github.workspace }}/sim/verilator/logs/ + + + custom_location_install: + name: Test installation with custom location + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h + - name: install + run: sudo ./bin/wally-tool-chain-install.sh --clean /home/riscv + - name: Upload instalation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-custom-location-install + path: /home/riscv/logs/ + - name: Update setup.sh with new $RISCV location + run: sed -i 's,/opt/riscv,/home/riscv,g' setup.sh + - name: make tests + run: | + source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini + make riscof + - name: regression + run: | + source setup.sh + regression-wally + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: installation-logs-${{ env.ARTIFACT_NAME }} From 521633698ca8a967e2fdf76b13a1d6c295effb5f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 7 Aug 2024 22:11:40 -0700 Subject: [PATCH 110/141] Add non-sudo and custom location installation tests --- .github/workflows/install.yml | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 74a9f58b1..a653fac5c 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -140,9 +140,18 @@ jobs: custom_location_install: - name: Test installation with custom location + name: Test installation with custom location ${{ matrix.path }} runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + path: ["/home/riscv"] steps: + - name: Unique name for Artifacts + id: prep_artifact_name + run: | + name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 with: submodules: recursive @@ -152,15 +161,15 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean /home/riscv + run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-custom-location-install - path: /home/riscv/logs/ + name: installation-logs-custom-location-install-${{ env.ARTIFACT_NAME }} + path: ${{ matrix.path }}/logs/ - name: Update setup.sh with new $RISCV location - run: sed -i 's,/opt/riscv,/home/riscv,g' setup.sh + run: sed -i 's,exit 1,export RISCV=${{ matrix.path }},g' setup.sh - name: make tests run: | source setup.sh @@ -174,5 +183,5 @@ jobs: uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-${{ env.ARTIFACT_NAME }} - path: /opt/riscv/logs/ + name: regression-logs-custom-location-install-${{ env.ARTIFACT_NAME }} + path: ${{ github.workspace }}/sim/verilator/logs/ From 59ee4cf7e4d0b5979cf1449653d520db2349fa57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 17 Aug 2024 09:43:18 -0700 Subject: [PATCH 111/141] Switch to new RISCOF humber of jobs in install test --- .github/workflows/install.yml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a653fac5c..771255ff7 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -86,7 +85,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -125,7 +123,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -173,7 +170,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | From 905521ef0ffbd2ad16ec66bbfd2b85106aeb494e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 30 Sep 2024 08:07:35 -0700 Subject: [PATCH 112/141] Update ci to use make --jobs --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 771255ff7..a84f93866 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -123,7 +123,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -170,7 +170,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh From 76503e517e8dec21049ffbac8f0cd94e2945bb2a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 8 Oct 2024 15:20:02 -0700 Subject: [PATCH 113/141] Running out of space --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a84f93866..b0e5255a8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof --jobs $(nproc --ignore 1) + make riscof - name: regression run: | source setup.sh From e50d85aa729885fa2cb1eba360734da391a0f6a1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 13:59:36 -0700 Subject: [PATCH 114/141] Trying to track down storage issue --- .github/workflows/install.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b0e5255a8..25762b4e1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -171,6 +171,10 @@ jobs: run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh From d389bb547fd795136a9d9b5e8f97f7ace8693431 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 21:54:28 -0700 Subject: [PATCH 115/141] Add storage checks --- .github/workflows/install.yml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 25762b4e1..5f58eef31 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -29,10 +29,18 @@ jobs: with: name: installation-logs-${{ matrix.os }} path: /opt/riscv/logs/ + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: make tests run: | source setup.sh make riscof + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh @@ -82,10 +90,18 @@ jobs: with: name: installation-logs-${{ env.ARTIFACT_NAME }} path: /opt/riscv/logs/ + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh From 7d6e283e041f3952da106f708fe16dc14fb547ce Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 20:41:00 -0700 Subject: [PATCH 116/141] Use precompiled riscv-gnu-toolchain binary for faster test --- bin/wally-tool-chain-install.sh | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..ba51ab5dc 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,19 +230,20 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then - cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - if [ "$clean" ]; then - cd "$RISCV" - rm -rf riscv-gnu-toolchain - fi +curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 +# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +# cd riscv-gnu-toolchain +# git reset --hard && git clean -f && git checkout b488ddb #&& git pull +# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] +# if [ "$clean" ]; then +# cd "$RISCV" +# rm -rf riscv-gnu-toolchain +# fi echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -else - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -fi +# else +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +# fi # elf2hex (https://github.com/sifive/elf2hex) From 19e15aee12db0cdf0ea676017caeab829de2363c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:17:20 -0700 Subject: [PATCH 117/141] Only clone needed submodules --- .github/workflows/install.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 5f58eef31..fea433ce1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -14,8 +14,8 @@ jobs: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -73,8 +73,8 @@ jobs: dnf install -y sudo git dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Fix git ownership run: git config --global --add safe.directory '*' - name: Free up storage @@ -119,8 +119,8 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -166,8 +166,8 @@ jobs: name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h From ec3907bfd75ea7ea3cf1c4093b830f9a6f3a4d4e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:30:18 -0700 Subject: [PATCH 118/141] Revert "Use precompiled riscv-gnu-toolchain binary for faster test" This reverts commit af480292f355e82c6bdc4cef040bdedc52dfd8fd. --- bin/wally-tool-chain-install.sh | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ba51ab5dc..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,20 +230,19 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 -# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then -# cd riscv-gnu-toolchain -# git reset --hard && git clean -f && git checkout b488ddb #&& git pull -# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] -# if [ "$clean" ]; then -# cd "$RISCV" -# rm -rf riscv-gnu-toolchain -# fi +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then + cd riscv-gnu-toolchain + git reset --hard && git clean -f && git checkout b488ddb #&& git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-gnu-toolchain + fi echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -# else -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -# fi +else + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +fi # elf2hex (https://github.com/sifive/elf2hex) From 77ed0b4ca5f2b50914092d6c6779efef6f01fd9f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:48:00 -0700 Subject: [PATCH 119/141] Fix git permissions --- .github/workflows/install.yml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index fea433ce1..d742b0ce4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -15,7 +15,9 @@ jobs: steps: - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -74,9 +76,9 @@ jobs: dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test - - name: Fix git ownership - run: git config --global --add safe.directory '*' + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -120,7 +122,9 @@ jobs: steps: - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -167,7 +171,9 @@ jobs: echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h From 62743d8237f9c7661683179f1943936265932bf9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 23:30:37 -0700 Subject: [PATCH 120/141] No buildroot and use precompiled gcc --- .github/workflows/install.yml | 8 ++++---- bin/wally-tool-chain-install.sh | 31 ++++++++++++++++--------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d742b0ce4..37eeda1ae 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -24,7 +24,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -85,7 +85,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -133,7 +133,7 @@ jobs: - name: install packages with sudo run: sudo ./bin/wally-package-install.sh - name: install - run: ./bin/wally-tool-chain-install.sh --clean + run: ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -180,7 +180,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..59e26eb66 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -228,21 +228,22 @@ fi # This book is tested with GCC 13.2.0 section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" -cd "$RISCV" -# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then - cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - if [ "$clean" ]; then - cd "$RISCV" - rm -rf riscv-gnu-toolchain - fi - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -else - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -fi +curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 +# cd "$RISCV" +# # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. +# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +# cd riscv-gnu-toolchain +# git reset --hard && git clean -f && git checkout b488ddb #&& git pull +# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] +# if [ "$clean" ]; then +# cd "$RISCV" +# rm -rf riscv-gnu-toolchain +# fi +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" +# else +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +# fi # elf2hex (https://github.com/sifive/elf2hex) From 361b4835a783152c9b7c835d91b8958ba201b24e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:23:07 -0700 Subject: [PATCH 121/141] revert precompiled gcc --- bin/wally-tool-chain-install.sh | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 59e26eb66..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -228,22 +228,21 @@ fi # This book is tested with GCC 13.2.0 section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" -curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 -# cd "$RISCV" -# # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then -# cd riscv-gnu-toolchain -# git reset --hard && git clean -f && git checkout b488ddb #&& git pull -# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] -# if [ "$clean" ]; then -# cd "$RISCV" -# rm -rf riscv-gnu-toolchain -# fi -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -# else -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -# fi +cd "$RISCV" +# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then + cd riscv-gnu-toolchain + git reset --hard && git clean -f && git checkout b488ddb #&& git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-gnu-toolchain + fi + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" +else + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +fi # elf2hex (https://github.com/sifive/elf2hex) From 86d0e13330c046475845a1a29605a592ffc28a8d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:48:39 -0700 Subject: [PATCH 122/141] Update submodules that are checked out --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 37eeda1ae..cfbb3a4d4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -17,7 +17,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -78,7 +78,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -124,7 +124,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -173,7 +173,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h From 732f5a932607dadec32fffcf7221c1525f76125a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 07:47:45 -0700 Subject: [PATCH 123/141] Add buildroot back to installation test --- .github/workflows/install.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index cfbb3a4d4..9b150f793 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -24,7 +24,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -38,7 +38,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: check storage run: | df -h @@ -85,7 +85,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -133,7 +133,7 @@ jobs: - name: install packages with sudo run: sudo ./bin/wally-package-install.sh - name: install - run: ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -180,7 +180,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot ${{ matrix.path }} + run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() From 4a337bf1d86d5afe15bb4efcc280ef042ba92699 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 22:34:16 -0700 Subject: [PATCH 124/141] Remove buildroot/output/build to save save in installation test --- .github/workflows/install.yml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9b150f793..7e912fb46 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,8 +41,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf /opt/riscv/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh @@ -102,8 +102,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf /opt/riscv/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh @@ -144,6 +144,10 @@ jobs: run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + sudo rm -rf /opt/riscv/buildroot/output/build + df -h - name: regression run: | source setup.sh @@ -195,8 +199,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf ${{ matrix.path }}/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh From f6d6537c7b673bb0caba4940a8ff2485dde2c69d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:11:17 -0700 Subject: [PATCH 125/141] Combine Ubuntu and Red Hat test installation workflows --- .github/workflows/install.yml | 124 ++++++++++++++-------------------- 1 file changed, 51 insertions(+), 73 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 7e912fb46..359868b3a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -5,106 +5,84 @@ defaults: shell: bash jobs: - ubuntu_install: - name: Test installation on ${{ matrix.os }} - runs-on: ${{ matrix.os }} + installation_test: + name: Test installation for ${{ matrix.name }} strategy: fail-fast: false matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] + include: + # Ubuntu Installations + - name: ubuntu-20.04 + os: ubuntu-20.04 + container: null + - name: ubuntu-22.04 + os: ubuntu-22.04 + container: null + - name: ubuntu-24.04 + os: ubuntu-24.04 + container: null + # Red Hat Installations + - name: rocky-8 + os: ubuntu-latest + image: rockylinux:8 + - name: rocky-9 + os: ubuntu-latest + image: rockylinux:9 + - name: almalinux-8 + os: ubuntu-latest + image: almalinux:8 + - name: almalinux-9 + os: ubuntu-latest + image: almalinux:9 + + runs-on: ${{ matrix.os }} + container: + image: ${{ matrix.image }} + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: + - name: Install Dependencies for Red Hat + if: ${{ matrix.image }} != null + run: | + dnf install -y sudo git + dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage + - name: Free Up Storage for Ubuntu + if: ${{ matrix.image }} == null run: | df -h ./.github/cli-space-cleanup.sh df -h - - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-${{ matrix.os }} - path: /opt/riscv/logs/ - - name: check storage - run: | - df -h - du -h --max-depth=1 - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf /opt/riscv/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-${{ matrix.os }} - path: ${{ github.workspace }}/sim/verilator/logs/ - - rhel_family_install: - name: Test installation on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] - steps: - - name: Unique name for Artifacts - id: prep_artifact_name - run: | - name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') - echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - - name: Install dependencies - run: | - dnf install -y sudo git - dnf install curl -y --allowerasing || true - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage + - name: Free Up Storage for Red Hat + if: ${{ matrix.image }} != null run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - - name: install + - name: Install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs + - name: Set Environment Variables + run: | + source setup.sh + echo "RISCV=$RISCV" >> "$GITHUB_ENV" + - name: Upload Installation Logs uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-${{ env.ARTIFACT_NAME }} - path: /opt/riscv/logs/ - - name: check storage - run: | - df -h - du -h --max-depth=1 + name: installation-logs-${{ matrix.name }} + path: $RISCV/logs/ - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) - - name: check storage + - name: Remove Buildroot to Save Space run: | sudo rm -rf /opt/riscv/buildroot/output/build df -h - - name: regression + - name: Regression run: | source setup.sh regression-wally @@ -112,7 +90,7 @@ jobs: uses: actions/upload-artifact@v4 if: always() with: - name: regression-logs-${{ env.ARTIFACT_NAME }} + name: regression-logs-${{ matrix.name }} path: ${{ github.workspace }}/sim/verilator/logs/ From 204661e286f61e8dc2f145678d1b5d61e59ad152 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:23:40 -0700 Subject: [PATCH 126/141] Fix github action syntax --- .github/workflows/install.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 359868b3a..e23e35d0a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,7 +41,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: - name: Install Dependencies for Red Hat - if: ${{ matrix.image }} != null + if: ${{ matrix.image != null }} run: | dnf install -y sudo git dnf install curl -y --allowerasing || true @@ -51,13 +51,13 @@ jobs: git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free Up Storage for Ubuntu - if: ${{ matrix.image }} == null + if: ${{ matrix.image == null }} run: | df -h ./.github/cli-space-cleanup.sh df -h - name: Free Up Storage for Red Hat - if: ${{ matrix.image }} != null + if: ${{ matrix.image != null }} run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" From f01a410cd50b89d97d4ea865b5ed89a14d9d490d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:37:18 -0700 Subject: [PATCH 127/141] Test variables --- .github/workflows/install.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e23e35d0a..a149c9750 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -40,6 +40,11 @@ jobs: image: ${{ matrix.image }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: + - name: Echo Variables + run: | + echo ${{ matrix.name }} + echo ${{ matrix.os }} + echo ${{ matrix.image }} - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | From 53d40869478fb2fbbb12c6dc854d9a0dc290b014 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:51:23 -0700 Subject: [PATCH 128/141] Combine storage clean up steps --- .github/workflows/install.yml | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a149c9750..0956ef23b 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -40,11 +40,6 @@ jobs: image: ${{ matrix.image }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: - - name: Echo Variables - run: | - echo ${{ matrix.name }} - echo ${{ matrix.os }} - echo ${{ matrix.image }} - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | @@ -55,17 +50,14 @@ jobs: run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free Up Storage for Ubuntu - if: ${{ matrix.image == null }} + - name: Free Up Storage run: | df -h - ./.github/cli-space-cleanup.sh - df -h - - name: Free Up Storage for Red Hat - if: ${{ matrix.image != null }} - run: | - df -h - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" + if [ -z ${{ matrix.image }} ]; then + ./.github/cli-space-cleanup.sh + else + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" + fi df -h - name: Install run: sudo ./bin/wally-tool-chain-install.sh --clean From 10f0e5eeeecac5336024ebdfcef35934b4f85a4d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 00:11:09 -0700 Subject: [PATCH 129/141] Combine remaining install tests --- .github/workflows/install.yml | 120 ++++++---------------------------- 1 file changed, 21 insertions(+), 99 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0956ef23b..9441215a8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -34,6 +34,16 @@ jobs: - name: almalinux-9 os: ubuntu-latest image: almalinux:9 + # User level installation + - name: user-install + os: ubuntu-latest + image: null + user: true + # Custom location installation + - name: custom-install + os: ubuntu-latest + image: null + riscv_path: /home/riscv runs-on: ${{ matrix.os }} container: @@ -60,9 +70,18 @@ jobs: fi df -h - name: Install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: | + if [ -z ${{ matrix.user }} ]; then + sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + else + sudo ./bin/wally-package-install.sh + . /bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + fi - name: Set Environment Variables run: | + if [ ! -z ${{ matrix.riscv_path }} ]; then + sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh + fi source setup.sh echo "RISCV=$RISCV" >> "$GITHUB_ENV" - name: Upload Installation Logs @@ -77,7 +96,7 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: Remove Buildroot to Save Space run: | - sudo rm -rf /opt/riscv/buildroot/output/build + sudo rm -rf $RISCV/buildroot/output/build df -h - name: Regression run: | @@ -89,100 +108,3 @@ jobs: with: name: regression-logs-${{ matrix.name }} path: ${{ github.workspace }}/sim/verilator/logs/ - - - user_install: - name: Test installation with user permissions - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - name: install packages with sudo - run: sudo ./bin/wally-package-install.sh - - name: install - run: ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-user-install - path: ~/riscv/logs/ - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf /opt/riscv/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-user-install - path: ${{ github.workspace }}/sim/verilator/logs/ - - - custom_location_install: - name: Test installation with custom location ${{ matrix.path }} - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - path: ["/home/riscv"] - steps: - - name: Unique name for Artifacts - id: prep_artifact_name - run: | - name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') - echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - - name: Upload instalation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-custom-location-install-${{ env.ARTIFACT_NAME }} - path: ${{ matrix.path }}/logs/ - - name: Update setup.sh with new $RISCV location - run: sed -i 's,exit 1,export RISCV=${{ matrix.path }},g' setup.sh - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf ${{ matrix.path }}/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-custom-location-install-${{ env.ARTIFACT_NAME }} - path: ${{ github.workspace }}/sim/verilator/logs/ From 43b2737a0357eacf30f6210dd1ed417102b8c9c8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 00:29:05 -0700 Subject: [PATCH 130/141] Fix typo --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9441215a8..0b462ab9e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -75,7 +75,7 @@ jobs: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} else sudo ./bin/wally-package-install.sh - . /bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} fi - name: Set Environment Variables run: | From 8fea89ac8758cce7655821d5c8ce7a277ffc2cc9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:30:05 -0700 Subject: [PATCH 131/141] Fix installation log path --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0b462ab9e..13ebaadc4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -89,7 +89,7 @@ jobs: if: always() with: name: installation-logs-${{ matrix.name }} - path: $RISCV/logs/ + path: ${{ env.RISCV }}/logs/ - name: make tests run: | source setup.sh From 58b4ecc211e0fa9c8c37eb0c0262721c4bdc7494 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:30:44 -0700 Subject: [PATCH 132/141] Skip regression for ubuntu 20.04 and red hat 8 because of broken verilator --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 13ebaadc4..62faca3dd 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -99,6 +99,7 @@ jobs: sudo rm -rf $RISCV/buildroot/output/build df -h - name: Regression + if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} run: | source setup.sh regression-wally From 771ed52c951774bc895a40c164c3b139c3c30bcd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:48:24 -0700 Subject: [PATCH 133/141] Add schedule to run weekly --- .github/workflows/install.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 62faca3dd..9c7f31a58 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,9 +1,12 @@ name: Installation -on: [workflow_dispatch, push] +on: + workflow_dispatch: + push: + schedule: + - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays defaults: run: shell: bash - jobs: installation_test: name: Test installation for ${{ matrix.name }} From bad3c7ab2efe700890d071e78ff8ec60f202deec Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 20:27:44 -0700 Subject: [PATCH 134/141] Only run installation test workflow for PRs that edit the installation scripts --- .github/workflows/install.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9c7f31a58..d93cd7811 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,7 +1,13 @@ name: Installation on: workflow_dispatch: - push: + pull_request: + branches: + - main + paths: + - 'bin/wally-tool-chain-install.sh' + - 'bin/wally-distro-check.sh' + - 'wally-package-install.sh' schedule: - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays defaults: From b0bc463c65bd2906e421e8aa69f783ec82a59433 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:05:35 -0700 Subject: [PATCH 135/141] Update gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 6aacdec2e..6afe74a2a 100644 --- a/.gitignore +++ b/.gitignore @@ -14,6 +14,7 @@ *.list # General directories to ignore +!.github/ .vscode/ __pycache__/ **/work* From af2edac7be4cd2ca400ff91f65fe65121b3e19f0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:06:39 -0700 Subject: [PATCH 136/141] Update gitignore for real --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 6afe74a2a..114d669ef 100644 --- a/.gitignore +++ b/.gitignore @@ -14,7 +14,7 @@ *.list # General directories to ignore -!.github/ +!.github/workflows/* .vscode/ __pycache__/ **/work* From ba243c8dbe82cfa21aa3232a9b4a58ff21e6b3c4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:07:17 -0700 Subject: [PATCH 137/141] Try updating gitignore again --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 114d669ef..f09faa3c0 100644 --- a/.gitignore +++ b/.gitignore @@ -14,10 +14,10 @@ *.list # General directories to ignore -!.github/workflows/* .vscode/ __pycache__/ **/work* +!.github/workflows/* /**/obj_dir* /**/gmon* From 7de44871ef7744a8529803843462d925f7535688 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:08:03 -0700 Subject: [PATCH 138/141] Finally got gitignore --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index f09faa3c0..31db4f885 100644 --- a/.gitignore +++ b/.gitignore @@ -17,7 +17,7 @@ .vscode/ __pycache__/ **/work* -!.github/workflows/* +!.github/* /**/obj_dir* /**/gmon* From b4447b393c3cf8fb20e1d4fe78e0ed334857d888 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:08:18 -0700 Subject: [PATCH 139/141] Add header to install.yml --- .github/workflows/install.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d93cd7811..e761fd2a3 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,3 +1,12 @@ +################################## +# install.yml +# jcarlin@hmc.edu October 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# GitHub Action to test the wally-tool-chain-install.sh script for all supported linux distributions +# and configurations. Runs weekly and on pull requests that modify the installation scripts. +################################## + name: Installation on: workflow_dispatch: From ffee13625b3b2ae0da3de7ea25084ed6fc8e5873 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:16:21 -0700 Subject: [PATCH 140/141] Add comments --- .github/workflows/install.yml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e761fd2a3..c0e1d6506 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,6 +8,8 @@ ################################## name: Installation + +# Run on PR that modifies the installation scripts, weekly, or manually on: workflow_dispatch: pull_request: @@ -19,9 +21,12 @@ on: - 'wally-package-install.sh' schedule: - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays + +# Use bash shell with extra GitHub Actions options for all jobs defaults: run: shell: bash + jobs: installation_test: name: Test installation for ${{ matrix.name }} @@ -63,21 +68,26 @@ jobs: image: null riscv_path: /home/riscv + # run on selected version of ubuntu or on ubuntu-latest with docker image runs-on: ${{ matrix.os }} container: image: ${{ matrix.image }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash # Allow for connection with host + steps: + # Docker images need git installed or the checkout action fails - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | dnf install -y sudo git dnf install curl -y --allowerasing || true + # Only clone submodules needed for standard tests/regression to save space - uses: actions/checkout@v4 - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet + # Free up space on the host machine, either from the container or the host - name: Free Up Storage run: | df -h @@ -87,6 +97,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" fi df -h + # Run main tool chain installation script, either as a user or system wide - name: Install run: | if [ -z ${{ matrix.user }} ]; then @@ -95,6 +106,7 @@ jobs: sudo ./bin/wally-package-install.sh ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} fi + # Set environment variables for the rest of the job - name: Set Environment Variables run: | if [ ! -z ${{ matrix.riscv_path }} ]; then @@ -102,25 +114,30 @@ jobs: fi source setup.sh echo "RISCV=$RISCV" >> "$GITHUB_ENV" + # Upload installation logs for debugging - name: Upload Installation Logs uses: actions/upload-artifact@v4 if: always() with: name: installation-logs-${{ matrix.name }} path: ${{ env.RISCV }}/logs/ + # Make riscof only as that is the only testsuite used by standard regression - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space - name: Remove Buildroot to Save Space run: | sudo rm -rf $RISCV/buildroot/output/build df -h + # Run standard regression, skipping distros that are known to be broken with Verilator - name: Regression if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} run: | source setup.sh regression-wally + # Upload regression logs for debugging - name: Upload regression logs uses: actions/upload-artifact@v4 if: always() From df86ecf128cecb8cb31771de9bed75560d30abc1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 22:01:28 -0700 Subject: [PATCH 141/141] Fix installation CI timezone --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c0e1d6506..dfa449526 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -20,7 +20,7 @@ on: - 'bin/wally-distro-check.sh' - 'wally-package-install.sh' schedule: - - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays + - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays # Use bash shell with extra GitHub Actions options for all jobs defaults: