diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh new file mode 100755 index 000000000..0f8de1619 --- /dev/null +++ b/.github/cli-space-cleanup.sh @@ -0,0 +1,65 @@ +#!/bin/bash +########################################### +## GitHub runner space cleanup +## +## Written: Jordan Carlin, jcarlin@hmc.edu +## Created: 30 June 2024 +## Modified: +## +## Purpose: Remove unnecessary packages/directories from GitHub Actions runner + +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Remove unnecessary packages +removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) +for pack in "${removePacks[@]}"; do + sudo apt-get purge -y "$pack" || true +done +sudo apt-get autoremove -y || true +sudo apt-get clean || true + +# Remove unnecessary directories +sudo rm -rf /usr/local/lib/android +sudo rm -rf /usr/share/dotnet +sudo rm -rf /usr/share/swift +sudo rm -rf /usr/share/miniconda +sudo rm -rf /usr/share/az* +sudo rm -rf /usr/share/gradle-* +sudo rm -rf /usr/share/sbt +sudo rm -rf /opt/ghc +sudo rm -rf /usr/local/.ghcup +sudo rm -rf /usr/local/share/powershell +sudo rm -rf /usr/local/lib/node_modules +sudo rm -rf /usr/local/julia* +sudo rm -rf /usr/local/share/chromium +sudo rm -rf /usr/local/share/vcpkg +sudo rm -rf /usr/local/games +sudo rm -rf /usr/local/sqlpackage +sudo rm -rf /usr/lib/google-cloud-sdk +sudo rm -rf /usr/lib/jvm +sudo rm -rf /usr/lib/mono +sudo rm -rf /usr/lib/R +sudo rm -rf /usr/lib/postgresql +sudo rm -rf /usr/lib/heroku +sudo rm -rf /usr/lib/firefox +sudo rm -rf /opt/hostedtoolcache + +# Clean up docker images +sudo docker image prune --all --force diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml new file mode 100644 index 000000000..dfa449526 --- /dev/null +++ b/.github/workflows/install.yml @@ -0,0 +1,146 @@ +################################## +# install.yml +# jcarlin@hmc.edu October 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# GitHub Action to test the wally-tool-chain-install.sh script for all supported linux distributions +# and configurations. Runs weekly and on pull requests that modify the installation scripts. +################################## + +name: Installation + +# Run on PR that modifies the installation scripts, weekly, or manually +on: + workflow_dispatch: + pull_request: + branches: + - main + paths: + - 'bin/wally-tool-chain-install.sh' + - 'bin/wally-distro-check.sh' + - 'wally-package-install.sh' + schedule: + - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays + +# Use bash shell with extra GitHub Actions options for all jobs +defaults: + run: + shell: bash + +jobs: + installation_test: + name: Test installation for ${{ matrix.name }} + strategy: + fail-fast: false + matrix: + include: + # Ubuntu Installations + - name: ubuntu-20.04 + os: ubuntu-20.04 + container: null + - name: ubuntu-22.04 + os: ubuntu-22.04 + container: null + - name: ubuntu-24.04 + os: ubuntu-24.04 + container: null + # Red Hat Installations + - name: rocky-8 + os: ubuntu-latest + image: rockylinux:8 + - name: rocky-9 + os: ubuntu-latest + image: rockylinux:9 + - name: almalinux-8 + os: ubuntu-latest + image: almalinux:8 + - name: almalinux-9 + os: ubuntu-latest + image: almalinux:9 + # User level installation + - name: user-install + os: ubuntu-latest + image: null + user: true + # Custom location installation + - name: custom-install + os: ubuntu-latest + image: null + riscv_path: /home/riscv + + # run on selected version of ubuntu or on ubuntu-latest with docker image + runs-on: ${{ matrix.os }} + container: + image: ${{ matrix.image }} + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash # Allow for connection with host + + steps: + # Docker images need git installed or the checkout action fails + - name: Install Dependencies for Red Hat + if: ${{ matrix.image != null }} + run: | + dnf install -y sudo git + dnf install curl -y --allowerasing || true + # Only clone submodules needed for standard tests/regression to save space + - uses: actions/checkout@v4 + - name: Clone Necessary Submodules + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet + # Free up space on the host machine, either from the container or the host + - name: Free Up Storage + run: | + df -h + if [ -z ${{ matrix.image }} ]; then + ./.github/cli-space-cleanup.sh + else + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" + fi + df -h + # Run main tool chain installation script, either as a user or system wide + - name: Install + run: | + if [ -z ${{ matrix.user }} ]; then + sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + else + sudo ./bin/wally-package-install.sh + ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + fi + # Set environment variables for the rest of the job + - name: Set Environment Variables + run: | + if [ ! -z ${{ matrix.riscv_path }} ]; then + sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh + fi + source setup.sh + echo "RISCV=$RISCV" >> "$GITHUB_ENV" + # Upload installation logs for debugging + - name: Upload Installation Logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ matrix.name }} + path: ${{ env.RISCV }}/logs/ + # Make riscof only as that is the only testsuite used by standard regression + - name: make tests + run: | + source setup.sh + make riscof --jobs $(nproc --ignore 1) + # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space + - name: Remove Buildroot to Save Space + run: | + sudo rm -rf $RISCV/buildroot/output/build + df -h + # Run standard regression, skipping distros that are known to be broken with Verilator + - name: Regression + if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} + run: | + source setup.sh + regression-wally + # Upload regression logs for debugging + - name: Upload regression logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: regression-logs-${{ matrix.name }} + path: ${{ github.workspace }}/sim/verilator/logs/ diff --git a/.gitignore b/.gitignore index 6aacdec2e..31db4f885 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,7 @@ .vscode/ __pycache__/ **/work* +!.github/* /**/obj_dir* /**/gmon* diff --git a/.gitmodules b/.gitmodules index b066104f7..eed0bb58f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,14 +20,11 @@ branch = dev [submodule "addins/branch-predictor-simulator"] path = addins/branch-predictor-simulator - url = https://github.com/ross144/branch-predictor-simulator -[submodule "addins/ahbsdc"] - path = addins/ahbsdc - url = https://github.com/JacobPease/ahbsdc.git + url = https://github.com/rosethompson/branch-predictor-simulator [submodule "addins/verilog-ethernet"] sparseCheckout = true path = addins/verilog-ethernet - url = https://github.com/ross144/verilog-ethernet.git + url = https://github.com/rosethompson/verilog-ethernet.git [submodule "cvw-arch-verif"] path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/addins/ahbsdc b/addins/ahbsdc deleted file mode 160000 index 33418c8dc..000000000 --- a/addins/ahbsdc +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3 diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 80cdee231..bbcba7864 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc +Subproject commit bbcba78647080dee82e96bc1b8ff9cd9a3cf7fa1 diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 20a65bf98..504edf439 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 23 October 2023 ## Modified: ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 5e0e7bc01..039e38a8b 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index 87648589f..27e0b1962 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index a0480f855..c9446a3b5 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -4,7 +4,7 @@ ## extractFunctionRadix.sh ## ## Written: Rose Thompson -## email: ross1728@gmail.com +## email: rose@rosethompson.net ## Created: March 1, 2021 ## Modified: March 10, 2021 ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 4408f2211..c0137916f 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ########################################### -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 20 September 2023 ## Modified: ## diff --git a/bin/requirements.txt b/bin/requirements.txt index 462898a60..d55bf7eda 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,12 +3,12 @@ lief>=0.14.1 Markdown>=3.6 matplotlib>=3.9.0 PyYAML>=5.2 -riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 -riscv-isac>=0.18.0 +riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac scikit-learn>=1.5.0 scipy>=1.13.0 -Sphinx>=7.3.7 +setuptools +Sphinx~=7.3.7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 53bc01c8b..d27e2a392 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -2,7 +2,7 @@ ########################################### ## Tool chain install script. ## -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 @@ -77,11 +77,17 @@ trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages # Check for clean flag -if [ "$1" == "--clean" ]; then +if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then clean=true shift fi +# Check for clean flag +if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then + no_buidroot=true + shift +fi + # Determine script directory to locate related scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" @@ -112,11 +118,27 @@ if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then exit 1 fi -# Create installation directory -mkdir -p "$RISCV"/logs +# Check available memory +total_mem=$(grep MemTotal < /proc/meminfo | awk '{print $2}') +total_mem_gb=$((total_mem / 1024 / 1024)) + +# Print system information echo "Running as root: $ROOT" echo "Installation path: $RISCV" +echo "Number of cores: $(nproc)" +echo "Total memory: $total_mem_gb GB" +# Reduce number of threads for systems with less than 8 GB of memory +if ((total_mem < 8400000 )) ; then + NUM_THREADS=1 + echo -e "${WARNING_COLOR}Detected less than or equal to 8 GB of memory. Using a single thread for compiling tools. This may take a while.${ENDC}" +fi + +# Print number of threads +echo "Using $NUM_THREADS thread(s) for compilation" + +# Create installation directory +mkdir -p "$RISCV"/logs # Install/update system packages if root. Otherwise, check that packages are already installed. STATUS="system packages" @@ -155,12 +177,11 @@ source "$RISCV"/riscv-python/bin/activate # activate python virtual environment # Install python packages, including RISCOF (https://github.com/riscv-software-src/riscof.git) # RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. STATUS="python packages" -pip install --upgrade pip && pip install -r "$dir"/requirements.txt +pip install --upgrade pip && pip install --upgrade -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" - # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then # Newer versin of glib required for QEMU. @@ -376,23 +397,27 @@ fi # Buildroot and Linux testvectors # Buildroot is used to boot a minimal versio of Linux on Wally. # Testvectors are generated using QEMU. -section_header "Installing Buildroot and Creating Linux testvectors" -STATUS="buildroot" -if [ -z "$LD_LIBRARY_PATH" ]; then - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ +if [ ! "$no_buidroot" ]; then + section_header "Installing Buildroot and Creating Linux testvectors" + STATUS="buildroot" + if [ -z "$LD_LIBRARY_PATH" ]; then + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + else + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + fi + cd "$dir"/../linux + if [ ! -e "$RISCV"/buildroot ]; then + make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" + elif [ ! -e "$RISCV"/linux-testvectors ]; then + echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" + make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" + else + echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + fi else - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ -fi -cd "$dir"/../linux -if [ ! -e "$RISCV"/buildroot ]; then - make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" -elif [ ! -e "$RISCV"/linux-testvectors ]; then - echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" - make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" -else - echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + echo -e "${OK_COLOR}Skipping Buildroot and Linux testvectors.${ENDC}" fi diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 8fe5d6622..3a04643ad 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -11,3 +11,6 @@ `include "RV32Zfh_coverage.svh" `include "RV32Zicond_coverage.svh" `include "RV32Zca_coverage.svh" +`include "RV32Zcb_coverage.svh" +`include "RV32ZcbM_coverage.svh" +`include "RV32ZcbZbb_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index f21eb2b1a..d1bbaedbb 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -16,3 +16,6 @@ // `include "RV64Zicbom_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" +`include "RV64Zcb_coverage.svh" +`include "RV64ZcbM_coverage.svh" +`include "RV64ZcbZbb_coverage.svh" \ No newline at end of file diff --git a/fpga/README.md b/fpga/README.md index dfa27479e..236bc7ddb 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,46 +1,57 @@ -The FPGA currently only targets the VCU118 board. +Wally supports the following boards -* Build Process +1. ArtyA7 +2. vcu108 +3. vcu118 (Do not recommend.) -cd generator -make +# Quick Start -* Description +## build FPGA -The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4, -axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks -and builds wally. fpga/src/fpgaTop.v is the top level which instanciates -wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic -analyzer) which provides the current instruction PCM, instrM, etc along with -a large number of debuging signals. +`cd generator +make ` -* Programming the flash card -You'll need to write the linux image to the flash card. Use the convert2bin.py -script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt -file from QEMU's preload to generate the binary. Then to copy - sudo dd if=ram.bin of=. +example +`make vcu108` -* Loading the FPGA +## Make flash card image +ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. +Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). -After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's -gui and open the WallyFPGA.xpr project file. Open the hardware manager under -program and debug. Open target and then program with the bit file. +`cd $WALLY/linux/sd-card` -* Test Run +This following script requires root. -Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide -status of the reset and ddr4 calibration. LED 7 should always be lit. -LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once -wally begins running. +`./flash-sd.sh -b -d ` -Next the bootloader program will copy the flash card into the DDR4 memory. -When this done the lower 5 LEDs will blink 5 times and then try to boot -the program loaded in the DDR4 memory at physical address 0x8000_0000. +example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc -* Connecting uart -You'll need to connect both usb cables. The first connects the FPGA programer -while the connect connects UART. UART is configured to use 57600 baud with -no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should -let you view the com port. +`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc` +Wait until the the script completes then remove the car. + +## FPGA setup + +For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card. + +For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards. + +Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch. +The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the +VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. + +`cd $WALLY/fpga/generator +vivado &` + +open the design in the current directory WallyFPGA.xpr. + +Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. + +## Connect to UART + +In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. + +`screen /dev/ttyUSB1 115200` + +Swap out the USB1 for USB0 or USB1 as needed. diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5151b0e77..3ca0c3360 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -47,7 +47,7 @@ if {$board=="ArtyA7"} { # read in all other rtl add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] +set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset] # define top level diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 1932038ad..3ac9c6f43 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvi daemon // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 31 May 2024 // Modified: 31 May 2024 // diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 0ecce067b..2bf6aee5e 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index cb350e08a..07c66ff95 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index a1e907913..db382ade1 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // wallypipelinedsocwrapper.sv // -// Written: Rose Thompson ross1728@gmail.com 16 June 2023 +// Written: Rose Thompson rose@rosethompson.net 16 June 2023 // Modified: // // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, diff --git a/fpga/zsbl/bios.S b/fpga/zsbl/bios.S new file mode 100644 index 000000000..a7283b38d --- /dev/null +++ b/fpga/zsbl/bios.S @@ -0,0 +1,102 @@ +#include "system.h" + +PERIOD = (SYSTEMCLOCK / 2) + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, (EXT_MEM_END - 8) + + li a0, 0x00000000 + li a1, EXT_MEM_BASE + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hart ID to a0 + li a1, FDT_ADDRESS # This is the device tree address + la a2, end_of_bios + li t0, EXT_MEM_BASE # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4c89d08cc..5855afb03 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cache.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 79b277a03..7f1904bbd 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheLRU.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 20 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 28cdc7440..1a39ad17a 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cachefsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 25 August 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index fb9d39f41..addf1a019 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheway // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 2c340c092..262992b52 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // subcachelineread.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 4 February 2022 // Modified: 20 January 2023 // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 572e824bb..f3fc676b0 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbcacheinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 821633f71..5e5406c1f 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 9461bd5c5..f81bfa67a 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 9080dbb83..fbd6fe3f6 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 1c4c360ec..9f644e1d3 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // controllerinput.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 31, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 8242d27e6..642eb6de4 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // abhmulticontroller // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 2e7b345f2..853acd09b 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ebufsmarb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2023 // Modified: 23 January 2023 // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index c0d314dd5..9fa09f4b6 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // arrs.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: November 12, 2021 // // Purpose: resets are typically asynchronous but need to be synchronized to diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 83b245485..558eb759a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // binencoder.sv // -// Written: ross1728@gmail.com November 14, 2022 +// Written: rose@rosethompson.net November 14, 2022 // // Purpose: one-hot to binary encoding. // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index d17262d22..9151a35d2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -2,7 +2,7 @@ // ram1p1r2be.sv // 1 port sram with byte enables // -// Written: ross1728@gmail.com +// Written: rose@rosethompson.net // Created: 3 May 2021 // Modified: 20 January 2023 // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index cdca14e38..84effae19 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -2,7 +2,7 @@ // ram1p1rwe.sv // 1 port sram. // -// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com) +// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net) // Created: 04 April 2023 // // Purpose: ram1p1wre, but without byte-enable. Used for icache data. diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 196aa0875..95840c2cc 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -2,7 +2,7 @@ // ram2p1r1wbe.sv // 2 port sram. // -// Written: ross1728@gmail.com May 3, 2021 +// Written: rose@rosethompson.net May 3, 2021 // Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 9b25feb65..91873c8e8 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // onehotdecoder.sv // -// Written: ross1728@gmail.com July 09, 2021 +// Written: rose@rosethompson.net July 09, 2021 // Modified: // // Purpose: Bin to one hot decoder. Power of 2 only. diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index d72f0e0d8..3bef28881 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 15 February 2021 // Modified: 25 January 2023 // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8d6a55d75..8b8793f27 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // bpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 12 February 2021 // Modified: 19 January 2023 // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e0ee0aaf4..6c6ace763 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: February 15, 2021 // Modified: 24 January 2023 // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 057993536..46702e6b1 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -2,7 +2,7 @@ // gshare.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) // Modified: 20 February 2023 diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index a0563d809..3f88494fe 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -2,7 +2,7 @@ // gsharebasic.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. // Modified: 20 February 2023 diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 01ebaca01..0b1992210 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // icpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: February 26, 2023 // Modified: February 26, 2023 // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index a2c7bda5a..e3d6ef8ed 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -2,7 +2,7 @@ // localaheadbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: local history branch predictor with ahead pipelining and SRAM memories. diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index b5634ef8a..5b2334a3d 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -2,7 +2,7 @@ // localbpbasic // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: Local history branch predictor. Basic implementation without any repair and flop memories. diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 5bb614d7f..e15c77f3c 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -2,7 +2,7 @@ // localrepairbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 15 April 2023 // // Purpose: Local history branch predictor with speculation and repair using CBH. diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index f59cef82b..90cdf4f58 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -2,7 +2,7 @@ // satCounter2.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 13, 2021 // Modified: // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 52a04d6e4..2277f8b9b 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -2,7 +2,7 @@ // twoBitPredictor.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 14, 2021 // Modified: // diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index ebebfbe4a..f85b60a5d 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // irom.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index c3c518913..f073398f3 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 28 January 2022 // Modified: 19 January 2023 // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index db37f4a66..f1e2e1892 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 26 October 2023 // Modified: 26 October 2023 // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 9c37b636c..cd87d70ac 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // atomic.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 31 January 2022 // Modified: 18 January 2023 // @@ -39,7 +39,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal - input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation + input logic LSUFlushW, // On FlushM or TLB miss ignore memory operation output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic SquashSCW, // Store conditional failed disable write to GPR output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC @@ -57,7 +57,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( // LRSC unit if (P.ZALRSC_SUPPORTED) begin - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + assign MemReadM = PreLSURWM[1] & ~LSUFlushW; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin assign SquashSCW = 0; diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 3fb6c81f6..f6530edc8 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // dtim.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index bc8852cf4..a1dd85d98 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -1,7 +1,7 @@ ///////////////////////////////////////////////////////////////////////////////////////////////////////// // lsu.sv // -// Written: David_Harris@hmc.edu, ross1728@gmail.com +// Written: David_Harris@hmc.edu, rose@rosethompson.net // Created: 9 January 2021 // Modified: 11 January 2023 // @@ -110,8 +110,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic BusStall; // Bus interface busy with multicycle operation - logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB + logic LSUBusStallM; // Bus interface busy with multicycle operation masked by HPTWFlushW logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall @@ -146,8 +145,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic DTLBWriteM; // Writes PTE and PageType to DTLB logic LSULoadAccessFaultM; // Load acces fault logic LSUStoreAmoAccessFaultM; // Store access fault - logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle - logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation + logic HPTWFlushW; // HPTW needs to flush operation + logic LSUFlushW; // HPTW or hazard unit flushes operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; @@ -200,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IHAdrM, .HPTWStall, .SelHPTW, - .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, + .HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF ); @@ -215,7 +214,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0; assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; end @@ -274,7 +273,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Pause IEU memory request if TLB miss. After TLB fill, replay request. // Discard memory request on pipeline flush - assign IgnoreRequest = IgnoreRequestTLB | FlushW; + assign LSUFlushW = HPTWFlushW | FlushW; if (P.DTIM_SUPPORTED) begin : dtim logic [P.PA_BITS-1:0] DTIMAdr; @@ -285,7 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DTIMMemRWM = SelDTIM ? LSURWM : 0; dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), - .DTIMAdr, .FlushW(IgnoreRequest), .WriteDataM(LSUWriteDataM), + .DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); end else assign DTIMReadDataWordM = '0; @@ -309,8 +308,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) logic FlushDCache; // Suppress d cache flush if there is an ITLB miss. - logic CacheStall; - logic [1:0] CacheBusRWTemp; logic BusCMOZero; logic [3:0] CacheCMOpM; logic BusAtomic; @@ -331,29 +328,26 @@ module lsu import cvw::*; #(parameter cvw_t P) ( cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( - .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(IgnoreRequest), + .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .WriteData(LSUWriteDataSpillM), .SelHPTW, - .CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), + .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), - .FetchBuffer, .CacheBusRW(CacheBusRWTemp), + .FetchBuffer, .CacheBusRW(CacheBusRW), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); - assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; - assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( - .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), + .HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), - .BusStall, .BusCommitted(BusCommittedM)); + .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM)); mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}), .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}), @@ -366,10 +360,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; - ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), + ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), - .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); // Mux between the 2 sources of read data, 0: Bus, 1: DTIM if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); @@ -381,12 +375,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; assign DCacheReadDataWordM = '0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = '0; + assign {LSUBusStallM, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; end - - assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations @@ -394,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, - .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 1'b0; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 7a0d2c4a6..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -58,7 +58,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( output logic [1:0] LSUAtomicM, output logic [2:0] LSUFunct3M, output logic [6:0] LSUFunct7M, - output logic IgnoreRequestTLB, + output logic HPTWFlushW, output logic SelHPTW, output logic HPTWStall, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, @@ -105,6 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic TakeHPTWFault; logic PBMTFaultM; logic HPTWFaultM; + logic ResetPTE; // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; @@ -143,7 +144,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // State flops flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE; - flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache + flopenr #(P.XLEN) PTEReg(clk, ResetPTE, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values // For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table @@ -274,23 +275,26 @@ module hptw import cvw::*; #(parameter cvw_t P) ( IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // First access in SV48 - L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; - L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; - L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - L0_RD: if (DCacheBusStallM) NextWalkerState = L0_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; @@ -300,7 +304,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. + assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); + + assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); diff --git a/src/rvvi/csrindextoaddr.sv b/src/rvvi/csrindextoaddr.sv index 0a843f491..4612dd4ee 100644 --- a/src/rvvi/csrindextoaddr.sv +++ b/src/rvvi/csrindextoaddr.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // csrindextoaddr.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 77c58f467..29a58d383 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // packetizer.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 21 May 2024 // Modified: 21 May 2024 // diff --git a/src/rvvi/priorityaomux.sv b/src/rvvi/priorityaomux.sv index d542c946f..7b119a81f 100644 --- a/src/rvvi/priorityaomux.sv +++ b/src/rvvi/priorityaomux.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // priorityaomux.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/regchangedetect.sv b/src/rvvi/regchangedetect.sv index 8becf867d..31d4ea1ec 100644 --- a/src/rvvi/regchangedetect.sv +++ b/src/rvvi/regchangedetect.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // regchangedetect.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index aa1c55aef..3e8170c93 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvisynth.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2024 // Modified: 23 January 2024 // diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv index 0a4269024..a4e74de91 100644 --- a/src/rvvi/triggergen.sv +++ b/src/rvvi/triggergen.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // triggergen.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: June 26, 2024 // Modified: June 26, 2024 // diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index cde584af2..5764ce26b 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // DCacheFlushFSM.sv // -// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com +// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index eac58f40a..5a14c84a4 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // functionName.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // // Purpose: decode name of function // diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index a9edb7892..6b026257a 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Log branch instructions, log instruction fetches, diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv index bd964d40d..f9c1f316c 100644 --- a/testbench/common/rvvitbwrapper.sv +++ b/testbench/common/rvvitbwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 24 July 2024 // // Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench. diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 9dbf6fa8b..f4b02a2e3 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // watchdog.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Detects if the processor is stuck and halts the simulation diff --git a/testbench/tests.vh b/testbench/tests.vh index a91aeda15..bef41ef22 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -60,6 +60,7 @@ string coverage64gc[] = '{ "tlbTP", "tlbMisaligned", "hptwAccessFault", + "nonleafpbmtfault", "amoAccessFault", "floatmisc", "ifuCamlineWrite", diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index 7c1bc3be1..e1a2ea49c 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -48,7 +48,32 @@ main: lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault add t0, t0, t2 - sw t1, 0(t0) + sw t1, 0(t0) + + j jumppoint + +jumppoint: +.align 6 # aligns to cache line size + sw t1, 0(t0) + sw t1, 4(t0) + sw t1, 8(t0) + sw t1, 12(t0) + sw t1, 16(t0) + sw t1, 20(t0) + sw t1, 24(t0) + sw t1, 28(t0) + sw t1, 32(t0) + sw t1, 36(t0) + sw t1, 40(t0) + sw t1, 44(t0) + sw t1, 48(t0) + sw t1, 52(t0) # this one causes a concurrent I$ miss with HPTW access exception (store access exception) + sw t1, 56(t0) + lw t3, 0(t0) + lw t3, 4(t0) + lw t3, 8(t0) + lw t3, 12(t0) + lw t3, 16(t0) fence.I diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S new file mode 100644 index 000000000..8a580ce02 --- /dev/null +++ b/tests/coverage/nonleafpbmtfault.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +// a load or store/amo page fault based on the original access type. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t2, 0x1000 + li t0, 0x8000001000 + + lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + li t1, 0x00008067 + add t0, t0, t2 + sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + + fence.I + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + .8byte 0x200044C1 + +.align 12 + .8byte 0x40000040200048C1 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x2000A0CF + .8byte 0x2000A4CF + .8byte 0x2000A8CF + .8byte 0x2000ACCF + + .8byte 0x2000B0CF + .8byte 0x2000B4CF + .8byte 0x2000B8CF + .8byte 0x2000BCCF + + .8byte 0x2000C0CF + .8byte 0x2000C4CF + .8byte 0x2000C8CF + .8byte 0x2000CCCF + + .8byte 0x2000D0CF + .8byte 0x2000D4CF diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S index 2edd1fc55..f3e3846f3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S index ceb3c3603..2df8c246f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index 31b11874b..e0c724aec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S index 97c3946eb..0e615a943 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 //