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../src/privileged/csrc.sv
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@ -44,12 +44,11 @@ module privmode (
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// PrivilegeMode FSM
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// PrivilegeMode FSM
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always_comb begin
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always_comb begin
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if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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if (`S_SUPPORTED & DelegateM)
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if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE;
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NextPrivilegeModeM = `S_MODE;
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else NextPrivilegeModeM = `M_MODE;
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else NextPrivilegeModeM = `M_MODE;
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end else if (mretM) NextPrivilegeModeM = STATUS_MPP;
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end else if (mretM) NextPrivilegeModeM = STATUS_MPP;
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else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else NextPrivilegeModeM = PrivilegeModeW;
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else NextPrivilegeModeM = PrivilegeModeW;
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end
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end
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flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
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flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
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@ -64,7 +64,7 @@ module trap (
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assign IntPendingM = |PendingIntsM;
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assign IntPendingM = |PendingIntsM;
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assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW;
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assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW;
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assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide.
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assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide.
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assign DelegateM = (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
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assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
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(PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
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(PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
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///////////////////////////////////////////
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///////////////////////////////////////////
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