From 6772bf9131f58ec0c482bea790c7e6a3241bd29b Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Mon, 1 Apr 2024 00:02:57 -0700 Subject: [PATCH 1/4] Bump the riscv-arch-test to the latest version with 0 fail. --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a52b016d..8a0cdceca 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d +Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b From c11d7ea55e93978fff6de97293e3b6e336f85925 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 1 Apr 2024 10:59:40 -0500 Subject: [PATCH 2/4] Fixed bug in the testbench which did not allow external memory to work correctly. --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee725c245..eef7e3f3b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -469,7 +469,7 @@ module testbench; assign SPIIn = 0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin From 929eb0430c779ef876df6ab95f30b281c9fbbae3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 3 Apr 2024 06:51:18 -0700 Subject: [PATCH 3/4] Testbench uses posedge control signals to speed up Verilator --- testbench/testbench.sv | 42 ++++++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ee725c245..60f14e48a 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -303,6 +303,24 @@ module testbench; assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; assign signature_size = end_signature_addr - begin_signature_addr; always @(posedge clk) begin + //////////////////////////////////////////////////////////////////////////////// + // Verify the test ran correctly by checking the memory against a known signature. + //////////////////////////////////////////////////////////////////////////////// + if(TestBenchReset) test = 1; + if (TEST == "coremark") + if (dut.core.priv.priv.EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end + if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin + $display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler."); + //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood. + end + + // modifications 4/3/24 kunlin & harris to speed up Verilator + // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block + end // added + always @(posedge SelectTest) // added if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else if(TEST == "buildroot") begin @@ -325,20 +343,8 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end - - //////////////////////////////////////////////////////////////////////////////// - // Verify the test ran correctly by checking the memory against a known signature. - //////////////////////////////////////////////////////////////////////////////// - if(TestBenchReset) test = 1; - if (TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin - $display("Benchmark: coremark is done."); - $stop; - end - if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin - $display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler."); - //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood. - end + + always @(posedge Validate) // added if(Validate) begin if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -374,10 +380,14 @@ module testbench; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); - $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage +`ifdef VERILATOR // this macro is defined when verilator is used + $finish; // V'lator needs $finish to terminate simulation. +`else + $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug +`endif end end - end +// end // removed //////////////////////////////////////////////////////////////////////////////// From 8755966f5049e77bc64ba0650314c78e80705864 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 3 Apr 2024 07:23:02 -0700 Subject: [PATCH 4/4] Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved --- testbench/testbench.sv | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a98e8c5b5..54cef0e97 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -319,8 +319,8 @@ module testbench; // modifications 4/3/24 kunlin & harris to speed up Verilator // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block - end // added - always @(posedge SelectTest) // added + //end // added + //always @(posedge SelectTest) // added if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else if(TEST == "buildroot") begin @@ -343,8 +343,14 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end - +`ifdef VERILATOR // this macro is defined when verilator is used + // Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is + // in the posedge clk block rather than a separate posedge Validate block. + // Until it is fixed, provide a silly posedge Validate block to keep Verilator happy. + // https://github.com/verilator/verilator/issues/4967 + end // restored always @(posedge Validate) // added +`endif if(Validate) begin if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -381,13 +387,16 @@ module testbench; if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); `ifdef VERILATOR // this macro is defined when verilator is used - $finish; // V'lator needs $finish to terminate simulation. + $finish; // Simulator Verilator needs $finish to terminate simulation. `else $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug `endif end end -// end // removed +`ifndef VERILATOR + // Remove this when issue 4967 is resolved and the posedge Validate logic above is removed + end +`endif //////////////////////////////////////////////////////////////////////////////// @@ -766,6 +775,8 @@ end logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; + + //$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time); // read .signature.output file and compare to check for errors if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};