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renamed endianswap

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This commit is contained in:
David Harris 2022-09-15 12:49:18 -07:00
parent 877cc63063
commit aa1f3ca2be
2 changed files with 4 additions and 4 deletions
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4
pipelined/src/lsu/bigendianswap.sv
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// bigendianswap.sv
// endianswap.sv
//
// Written: David_Harris@hmc.edu 7 May 2022
// Modified:
@ -30,7 +30,7 @@
`include "wally-config.vh"
module bigendianswap #(parameter LEN=`XLEN) (
module endianswap #(parameter LEN=`XLEN) (
input logic BigEndianM,
input logic [LEN-1:0] a,
output logic [LEN-1:0] y);

4
pipelined/src/lsu/lsu.sv
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@ -347,8 +347,8 @@ module lsu (
// swap the bytes when read from big-endian memory
/////////////////////////////////////////////////////////////////////////////////////////////
if (`BIGENDIAN_SUPPORTED) begin:endian
bigendianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
end else begin
assign LSUWriteDataM = LittleEndianWriteDataM;
assign LittleEndianReadDataWordM = ReadDataWordMuxM;