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https://github.com/openhwgroup/cvw
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renamed endianswap
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// bigendianswap.sv
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// endianswap.sv
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//
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//
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// Written: David_Harris@hmc.edu 7 May 2022
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// Written: David_Harris@hmc.edu 7 May 2022
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// Modified:
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// Modified:
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@ -30,7 +30,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module bigendianswap #(parameter LEN=`XLEN) (
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module endianswap #(parameter LEN=`XLEN) (
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input logic BigEndianM,
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input logic BigEndianM,
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input logic [LEN-1:0] a,
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input logic [LEN-1:0] a,
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output logic [LEN-1:0] y);
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output logic [LEN-1:0] y);
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@ -347,8 +347,8 @@ module lsu (
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// swap the bytes when read from big-endian memory
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// swap the bytes when read from big-endian memory
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (`BIGENDIAN_SUPPORTED) begin:endian
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if (`BIGENDIAN_SUPPORTED) begin:endian
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bigendianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
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endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
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bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
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endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
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end else begin
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end else begin
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assign LSUWriteDataM = LittleEndianWriteDataM;
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assign LSUWriteDataM = LittleEndianWriteDataM;
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assign LittleEndianReadDataWordM = ReadDataWordMuxM;
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assign LittleEndianReadDataWordM = ReadDataWordMuxM;
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