From 8d8d2aabc25a3e1fac9f4509f9a3470f210f85bc Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 15 Jun 2021 19:24:24 -0400 Subject: [PATCH 02/30] fixed incorrect expectation fof CLINT spec --- wally-pipelined/testgen/privileged/testgen-CAUSE.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 0bca336cf..2df328927 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -69,7 +69,8 @@ def writeVectors(storecmd, returningInstruction): csrrc x0, {fromMode}status, x1 la x18, {clintAddr} - {storecmd} x0, 0(x18) + li x1, -1 + {storecmd} x1, 0(x18) """) # Page 6 of unpriviledged spec From 7a652139b5d1a68c0a17aa1656828401c3013177 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 16 Jun 2021 17:37:08 -0400 Subject: [PATCH 03/30] mcause test fixes and s-mode interrupt bugfix --- wally-pipelined/src/privileged/csr.sv | 3 +-- wally-pipelined/src/privileged/privileged.sv | 2 +- wally-pipelined/src/privileged/trap.sv | 4 ++-- wally-pipelined/src/uncore/clint.sv | 20 +++++++++---------- .../testgen/privileged/testgen-CAUSE.py | 4 +++- 5 files changed, 17 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index fa1f49814..a42e29376 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -55,7 +55,7 @@ module csr #(parameter output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, + output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MXR, STATUS_SUM, output logic STATUS_MPRV, @@ -80,7 +80,6 @@ module csr #(parameter logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; logic [11:0] CSRAdrM; - logic [11:0] SIP_REGW, SIE_REGW; //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 1b85d151a..4f4ecd70f 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -96,7 +96,7 @@ module privileged ( logic [1:0] STATUS_MPP; logic STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it? logic STATUS_MIE, STATUS_SIE; - logic [11:0] MIP_REGW, MIE_REGW; + logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; logic md, sd; diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 93475b9d3..af4f17305 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -35,7 +35,7 @@ module trap ( input logic mretM, sretM, uretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, - input logic [11:0] MIP_REGW, MIE_REGW, + input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, input logic STATUS_MIE, STATUS_SIE, input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, @@ -58,7 +58,7 @@ module trap ( // Determine pending enabled interrupts assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 - assign PendingIntsM = (MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888) | ({12{SIntGlobalEnM}} & 12'h222); + assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM; // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index e3b22a869..df4c1e8fa 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -27,22 +27,22 @@ `include "wally-config.vh" module clint ( - input logic HCLK, HRESETn, - input logic HSELCLINT, - input logic [15:0] HADDR, - input logic HWRITE, - input logic [`XLEN-1:0] HWDATA, - output logic [`XLEN-1:0] HREADCLINT, - output logic HRESPCLINT, HREADYCLINT, + input logic HCLK, HRESETn, + input logic HSELCLINT, + input logic [15:0] HADDR, + input logic HWRITE, + input logic [`XLEN-1:0] HWDATA, input logic HREADY, - input logic [1:0] HTRANS, - output logic TimerIntM, SwIntM); + input logic [1:0] HTRANS, + output logic [`XLEN-1:0] HREADCLINT, + output logic HRESPCLINT, HREADYCLINT, + output logic TimerIntM, SwIntM); logic [63:0] MTIMECMP, MTIME; logic MSIP; logic [15:0] entry, entryd; - logic memread, memwrite; + logic memread, memwrite; logic initTrans; assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00); diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 2df328927..0ab0128b4 100755 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -53,7 +53,7 @@ def writeVectors(storecmd, returningInstruction): csrrs x0, {fromMode}status, x1 la x18, {clintAddr} - lw x11, 0(x18) + {loadcmd} x11, 0(x18) li x1, 0x3fffffffffffffff {storecmd} x1, 0(x18) @@ -310,9 +310,11 @@ for xlen in xlens: formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x if (xlen == 32): storecmd = "sw" + loadcmd = "lw" wordsize = 4 else: storecmd = "sd" + loadcmd = "ld" wordsize = 8 # testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"] From 7de660f8aa24efbf83dc3097d282f24761b65428 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 00:50:02 -0400 Subject: [PATCH 04/30] still not sure if QEMU workaround is correct, but here is all linux progress so far --- .gitignore | 4 +- .../linux-testgen/logAllBuildroot.sh | 13 +- .../linux-testgen/parse_gdb_output.py | 128 +++++++++--------- wally-pipelined/linux-testgen/parse_qemu.py | 14 +- 4 files changed, 81 insertions(+), 78 deletions(-) diff --git a/.gitignore b/.gitignore index 7f65a18a6..1b19857de 100644 --- a/.gitignore +++ b/.gitignore @@ -16,8 +16,8 @@ wlft* /imperas-riscv-tests/FunctionRadix.addr /imperas-riscv-tests/ProgramMap.txt /imperas-riscv-tests/logs -/wally-pipelined/busybear-testgen/gdbcombined.txt -/wally-pipelined/busybear-testgen/first10.txt +/wally-pipelined/linux-testgen/qemu_output.txt +/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt *.o *.d testsBP/*/*/*.elf* diff --git a/wally-pipelined/linux-testgen/logAllBuildroot.sh b/wally-pipelined/linux-testgen/logAllBuildroot.sh index dfb5205a5..df8b506a8 100755 --- a/wally-pipelined/linux-testgen/logAllBuildroot.sh +++ b/wally-pipelined/linux-testgen/logAllBuildroot.sh @@ -2,25 +2,26 @@ # Uncomment this version for GDB/QEMU debugging # - Opens up GDB interactively # - Logs raw QEMU output to qemu_output.txt -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> /mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb +#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> qemu_output.txt) & riscv64-unknown-elf-gdb # Uncomment this version to generate qemu_output.txt # - Uses GDB script # - Logs raw QEMU output to qemu_output.txt -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>/mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog +#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog_debug # Uncomment this version for parse_qemu.py debugging # - Uses qemu_output.txt # - Makes qemu_in_gdb_format.txt # - Logs parse_qemu.py's simulated gdb output to qemu_in_gdb_format.txt -#cat /mnt/scratch/wally_linux_output/qemu_output.txt | ./parse_qemu.py >/mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt +#cat qemu_output.txt | ./parse_qemu.py >qemu_in_gdb_format.txt +#cat qemu_output.txt | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" # Uncomment this version for parse_gdb_output.py debugging # - Uses qemu_in_gdb_format.txt # - Logs info needed by buildroot testbench -cat /mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" +#cat qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/" # =========== Just Do the Thing ========== -# Uncomment this version for the whole thing (if it works ha ha_ +# Uncomment this version for the whole thing # - Logs info needed by buildroot testbench -#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog +(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog diff --git a/wally-pipelined/linux-testgen/parse_gdb_output.py b/wally-pipelined/linux-testgen/parse_gdb_output.py index 5ae62b326..739a97e31 100755 --- a/wally-pipelined/linux-testgen/parse_gdb_output.py +++ b/wally-pipelined/linux-testgen/parse_gdb_output.py @@ -27,7 +27,7 @@ try: readType = '' lastReadType = '' readLoc = '' - instrStart = -1 + lineOffset = -1 lastRegs = '' curRegs = '' storeReg = '' @@ -40,10 +40,12 @@ try: for l in fileinput.input('-'): l = l.split("#")[0].rstrip() if l.startswith('=>'): + # Begin new instruction instrs += 1 storeAMO = '' if instrs % 10000 == 0: print(instrs) + # Instr in human assembly wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2]))) if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l: currentRead = l.split()[-1].split(',')[0] @@ -53,7 +55,6 @@ try: readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1] readType = l.split()[-2] if 'amo' in l: - #print(l) currentRead = l.split()[-1].split(',')[0] readOffset = "0" readLoc = l.split()[-1].split('(')[1][:-1] @@ -63,7 +64,6 @@ try: storeReg = l.split()[-1].split(',')[1] storeAMO = l.split()[-2] if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l: - #print(l) s = l.split('#')[0].split()[-1] storeReg = s.split(',')[0] if len(s.split(',')) < 2: @@ -74,17 +74,19 @@ try: print(l) storeOffset = s.split(',')[1].split('(')[0] storeLoc = s.split(',')[1].split('(')[1][:-1] - instrStart = 0 - elif instrStart != -1: - instrStart += 1 - if instrStart == 1: + lineOffset = 0 + elif lineOffset != -1: + lineOffset += 1 + if lineOffset == 1: + # Instr in hex comes one line after the instruction wPC.write('{}\n'.format(l.split()[-1][2:])) - elif instrStart < 34: + # As well as instr address + wPC.write('{}\n'.format(l.split()[0][2:].strip(":"))) + elif lineOffset <= (1+32): + # Next 32 lines are the Register File if lastRead == l.split()[0]: readData = int(l.split()[1][2:], 16) readData <<= (8 * (lastReadLoc % 8)) - #if(lastReadLoc % 8 != 0 and ('lw' in lastReadType or 'lb' in lastReadType)): - # readData <<= 32 wMem.write('{:x}\n'.format(readData)) if readLoc == l.split()[0]: readLoc = l.split()[1][2:] @@ -92,16 +94,12 @@ try: storeReg = l.split()[1] if storeLoc == l.split()[0]: storeLoc = l.split()[1][2:] - if instrStart > 2: - #print(l) - #print(instrStart) + if lineOffset > (1+1): + # Start logging x1 onwards (we don't care about x0) curRegs += '{}\n'.format(l.split()[1][2:]) - elif instrStart < 35: - #print("----------") - #print(l.split()[1][2:]) - wPC.write('{}\n'.format(l.split()[1][2:])) - #print(l.split()[1][2:]) - if any([c == l.split()[0] for c in csrs]): + #elif "pc" in l: + # wPC.write('{}\n'.format(l.split()[1][2:])) + if any([csr == l.split()[0] for csr in csrs]): if l.split()[0] in curCSRs: if curCSRs[l.split()[0]] != l.split()[1]: if firstCSR: @@ -112,51 +110,53 @@ try: wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:])) curCSRs[l.split()[0]] = l.split()[1] if '-----' in l: # end of each cycle - if curRegs != lastRegs: - if lastRegs == '': - wReg.write(curRegs) - else: - for i in range(32): - if curRegs.split('\n')[i] != lastRegs.split('\n')[i]: - wReg.write('{}\n'.format(i+1)) - wReg.write('{}\n'.format(curRegs.split('\n')[i])) - break - lastRegs = curRegs - if lastAMO != '': - if 'amoadd' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:] - elif 'amoand' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:] - elif 'amoor' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:] - elif 'amoswap' in lastAMO: - lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:] - else: - print(lastAMO) - exit() - wMemW.write('{}\n'.format(lastStoreReg)) - wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16))) - if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '': - storeLocOffset = int(storeOffset,10) + int(storeLoc, 16) - #wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8)))) - wMemW.write('{}\n'.format(storeReg[2:])) - wMemW.write('{:x}\n'.format(storeLocOffset)) - if readOffset != '' and readLoc != '': - wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16))) - lastReadLoc = int(readOffset,10) + int(readLoc, 16) - lastReadType = readType - readOffset = '' - readLoc = '' - curRegs = '' - instrStart = -1 - lastRead = currentRead - currentRead = '' - lastStoreReg = storeReg - lastStoreLoc = storeLoc - storeReg = '' - storeOffset = '' - storeLoc = '' - lastAMO = storeAMO + if curRegs != lastRegs: + if lastRegs == '': + wReg.write(curRegs) + else: + for i in range(32): + if curRegs.split('\n')[i] != lastRegs.split('\n')[i]: + wReg.write('{}\n'.format(i+1)) + wReg.write('{}\n'.format(curRegs.split('\n')[i])) + break + lastRegs = curRegs + if lastAMO != '': + if 'amoadd' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:] + elif 'amoand' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:] + elif 'amoor' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:] + elif 'amoswap' in lastAMO: + lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:] + else: + print(lastAMO) + exit() + #print('lastStoreReg {}\n'.format(lastStoreReg)) + #print('lastStoreLoc '+str(lastStoreLoc)) + wMemW.write('{}\n'.format(lastStoreReg)) + wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16))) + if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '': + storeLocOffset = int(storeOffset,10) + int(storeLoc, 16) + #wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8)))) + wMemW.write('{}\n'.format(storeReg[2:])) + wMemW.write('{:x}\n'.format(storeLocOffset)) + if readOffset != '' and readLoc != '': + wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16))) + lastReadLoc = int(readOffset,10) + int(readLoc, 16) + lastReadType = readType + readOffset = '' + readLoc = '' + curRegs = '' + lineOffset = -1 + lastRead = currentRead + currentRead = '' + lastStoreReg = storeReg + lastStoreLoc = storeLoc + storeReg = '' + storeOffset = '' + storeLoc = '' + lastAMO = storeAMO except (FileNotFoundError): diff --git a/wally-pipelined/linux-testgen/parse_qemu.py b/wally-pipelined/linux-testgen/parse_qemu.py index 91d45800c..c7f31fb22 100755 --- a/wally-pipelined/linux-testgen/parse_qemu.py +++ b/wally-pipelined/linux-testgen/parse_qemu.py @@ -39,12 +39,14 @@ def parseCSRs(l): csr = l.split()[0] val = int(l.split()[1],16) if inPageFault: - if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): - # We do update some CSRs - CSRs[csr] = val - else: - # Others we preserve until changed later - pageFaultCSRs[csr] = val + # Not sure if these CSRs should be updated or not during page fault. + #if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): + # # We do update some CSRs + # CSRs[csr] = val + #else: + # # Others we preserve until changed later + # pageFaultCSRs[csr] = val + pageFaultCSRs[csr] = val elif pageFaultCSRs and (csr in pageFaultCSRs): if (val != pageFaultCSRs[csr]): del pageFaultCSRs[csr] From e93e528aa1d66039e9fd0e03c0e2241cb603271f Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 05:18:14 -0400 Subject: [PATCH 05/30] changed parsedCSRs2] to parsedCSRs --- wally-pipelined/testbench/testbench-linux.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 52c40060c..55ba21b4f 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -162,7 +162,7 @@ module testbench(); // read CSR trace file integer data_file_csr, scan_file_csr; initial begin - data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); + data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs.txt"}, "r"); if (data_file_csr == 0) begin $display("file couldn't be opened"); $stop; From 0647094e73128b3793429172152558168f4e155e Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 05:19:36 -0400 Subject: [PATCH 06/30] PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable --- wally-pipelined/src/privileged/csrm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index bbf765dc5..209eadd8b 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -172,7 +172,7 @@ module csrm #(parameter // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop generate genvar i; - for (i = 0; i < `PMP_ENTRIES-1; i++) begin: pmp_flop + for (i = 0; i < `PMP_ENTRIES; i++) begin: pmp_flop flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); end endgenerate From 832e4fc7e31f53a3ca342af0274bebad92721716 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 08:37:37 -0400 Subject: [PATCH 07/30] making linux waveforms more useful --- wally-pipelined/regression/wally-buildroot.do | 2 +- wally-pipelined/regression/wally-busybear.do | 2 +- .../wave-dos/bens-busybear-waves.do | 64 --------- .../{busybear-waves.do => linux-waves.do} | 128 ++++++++---------- wally-pipelined/testbench/testbench-linux.sv | 24 +++- 5 files changed, 76 insertions(+), 144 deletions(-) delete mode 100644 wally-pipelined/regression/wave-dos/bens-busybear-waves.do rename wally-pipelined/regression/wave-dos/{busybear-waves.do => linux-waves.do} (53%) diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do index c212831e8..21767385e 100644 --- a/wally-pipelined/regression/wally-buildroot.do +++ b/wally-pipelined/regression/wally-buildroot.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/busybear-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation run -all diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 3638a7755..11876dded 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/bens-busybear-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/regression/wave-dos/bens-busybear-waves.do b/wally-pipelined/regression/wave-dos/bens-busybear-waves.do deleted file mode 100644 index 0d672167c..000000000 --- a/wally-pipelined/regression/wave-dos/bens-busybear-waves.do +++ /dev/null @@ -1,64 +0,0 @@ -# busybear-waves.do -restart -f -delete wave /* -view wave - -add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/ICacheStallF -add wave /testbench/dut/hart/StallF -add wave /testbench/dut/hart/StallD -add wave /testbench/dut/hart/StallE -add wave /testbench/dut/hart/StallM -add wave /testbench/dut/hart/StallW -add wave /testbench/dut/hart/FlushD -add wave /testbench/dut/hart/FlushE -add wave /testbench/dut/hart/FlushM -add wave /testbench/dut/hart/FlushW -add wave -divider - -add wave /testbench/clk -add wave /testbench/reset -add wave -divider - -add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/PCtext -add wave -hex /testbench/pcExpected -add wave -hex /testbench/dut/hart/ifu/PCD -add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCE -add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -#add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCM -add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -add wave /testbench/dut/uncore/dtim/memwrite -add wave -hex /testbench/dut/uncore/HADDR -add wave -hex /testbench/dut/uncore/HWDATA -add wave -divider -add wave -hex /testbench/PCW -add wave -hex /testbench/InstrW -add wave /testbench/InstrWName -add wave /testbench/dut/hart/ieu/dp/RegWriteW -add wave -hex /testbench/dut/hart/ieu/dp/ResultW -add wave -hex /testbench/dut/hart/ieu/dp/RdW -add wave -divider - -# appearance -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 150 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal \ No newline at end of file diff --git a/wally-pipelined/regression/wave-dos/busybear-waves.do b/wally-pipelined/regression/wave-dos/linux-waves.do similarity index 53% rename from wally-pipelined/regression/wave-dos/busybear-waves.do rename to wally-pipelined/regression/wave-dos/linux-waves.do index 00df1087a..58da63301 100644 --- a/wally-pipelined/regression/wave-dos/busybear-waves.do +++ b/wally-pipelined/regression/wave-dos/linux-waves.do @@ -1,58 +1,66 @@ -# busybear-waves.do - +# linux-waves.do restart -f delete wave /* view wave --- display input and output signals as hexidecimal values -# Diplays All Signals recursively +add wave -divider add wave /testbench/clk add wave /testbench/reset -add wave -divider -add wave -hex /testbench/PCtext + +add wave -divider Stalls_and_Flushes +add wave /testbench/dut/hart/StallF +add wave /testbench/dut/hart/StallD +add wave /testbench/dut/hart/StallE +add wave /testbench/dut/hart/StallM +add wave /testbench/dut/hart/StallW +add wave -group stall_srcs /testbench/dut/hart/DataStall +add wave -group stall_srcs /testbench/dut/hart/ICacheStallF +add wave /testbench/dut/hart/FlushD +add wave /testbench/dut/hart/FlushE +add wave /testbench/dut/hart/FlushM +add wave /testbench/dut/hart/FlushW + +add wave -divider F +add wave -hex /testbench/dut/hart/ifu/PCF +add wave -divider D add wave -hex /testbench/pcExpected add wave -hex /testbench/dut/hart/ifu/PCD +add wave -hex /testbench/PCtextD +add wave /testbench/InstrDName add wave -hex /testbench/dut/hart/ifu/InstrD -add wave -hex /testbench/dut/hart/ifu/StallD -add wave -hex /testbench/dut/hart/ifu/FlushD -add wave -hex /testbench/dut/hart/ifu/StallE -add wave -hex /testbench/dut/hart/ifu/FlushE -add wave -hex /testbench/dut/hart/ifu/InstrRawD -add wave /testbench/CheckInstrD -add wave /testbench/lastCheckInstrD -add wave /testbench/speculative -add wave /testbench/lastPC2 -add wave -divider -add wave -divider -add wave /testbench/dut/uncore/HSELBootTim -add wave /testbench/dut/uncore/HSELTim -add wave /testbench/dut/uncore/HREADTim -add wave /testbench/dut/uncore/dtim/HREADTim0 -add wave /testbench/dut/uncore/HREADYTim -add wave -divider -add wave /testbench/dut/uncore/HREADBootTim -add wave /testbench/dut/uncore/bootdtim/HREADTim0 -add wave /testbench/dut/uncore/HREADYBootTim -add wave /testbench/dut/uncore/HADDR -add wave /testbench/dut/uncore/HRESP -add wave /testbench/dut/uncore/HREADY -add wave /testbench/dut/uncore/HRDATA -#add wave -hex /testbench/dut/hart/priv/csr/MTVEC_REG -#add wave -hex /testbench/dut/hart/priv/csr/MSTATUS_REG -#add wave -hex /testbench/dut/hart/priv/csr/SCOUNTEREN_REG -#add wave -hex /testbench/dut/hart/priv/csr/MIE_REG -#add wave -hex /testbench/dut/hart/priv/csr/MIDELEG_REG -#add wave -hex /testbench/dut/hart/priv/csr/MEDELEG_REG -add wave -divider -# registers! +add wave -hex /testbench/dut/hart/ieu/c/InstrValidD +add wave -divider E +add wave -hex /testbench/dut/hart/ifu/PCE +add wave -hex /testbench/PCtextE +add wave /testbench/InstrEName +add wave -hex /testbench/dut/hart/ifu/InstrE +add wave -hex /testbench/dut/hart/ieu/c/InstrValidE +add wave -hex /testbench/dut/hart/ieu/dp/SrcAE +add wave -hex /testbench/dut/hart/ieu/dp/SrcBE +add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE +add wave -divider M +add wave -hex /testbench/dut/hart/ifu/PCM +add wave -hex /testbench/PCtextM +add wave /testbench/InstrMName +add wave -hex /testbench/dut/hart/ifu/InstrM +add wave -hex /testbench/dut/hart/ieu/c/InstrValidM +add wave /testbench/dut/uncore/dtim/memwrite +add wave -hex /testbench/dut/uncore/HADDR +add wave -hex /testbench/HWRITE +add wave -hex /testbench/dut/uncore/HWDATA +add wave -hex /testbench/HRDATA +add wave -hex /testbench/readAdrExpected +add wave -divider W +add wave -hex /testbench/PCW +add wave -hex /testbench/PCtextW +add wave -hex /testbench/dut/hart/ieu/c/InstrValidW +add wave /testbench/dut/hart/ieu/dp/RegWriteW +add wave -hex /testbench/dut/hart/ieu/dp/ResultW +add wave -hex /testbench/dut/hart/ieu/dp/RdW + +add wave -divider RegFile add wave -hex /testbench/regExpected add wave -hex /testbench/regNumExpected -add wave -hex /testbench/HWRITE -add wave -hex /testbench/dut/hart/MemRWM[1] -add wave -hex /testbench/HWDATA -add wave -hex /testbench/HRDATA -add wave -hex /testbench/HADDR -add wave -hex /testbench/readAdrExpected add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3] @@ -84,36 +92,10 @@ add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31] -add wave /testbench/InstrFName -add wave -hex /testbench/dut/hart/ifu/PCD -#add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -#add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCE -##add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -#add wave /testbench/dut/hart/ieu/dp/PCSrcE -#add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCM -##add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -#add wave /testbench/dut/hart/dmem/dtim/memwrite -#add wave -hex /testbench/dut/hart/dmem/AdrM -#add wave -hex /testbench/dut/hart/dmem/WriteDataM -#add wave -divider -add wave -hex /testbench/PCW -##add wave -hex /testbench/dut/hart/ifu/InstrW -add wave /testbench/InstrWName -#add wave /testbench/dut/hart/ieu/dp/RegWriteW -#add wave -hex /testbench/dut/hart/ieu/dp/ResultW -#add wave -hex /testbench/dut/hart/ieu/dp/RdW -#add wave -divider -##add ww + +add wave -divider add wave -hex -r /testbench/* -# + # appearance TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {100 ps} diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 55ba21b4f..6cf20e674 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -473,7 +473,21 @@ module testbench(); end end - string PCtext, PCtext2; + string PCtextD,PCtextE,PCtextM,PCtext2; + always_ff @(posedge clk, posedge reset) + if (reset) begin + PCtextE <= #1 "(reset)"; + PCtextM <= #1 "(reset)"; + end else begin + if (~dut.hart.StallE) + if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; + else PCtextE <= #1 PCtextD; + if (~dut.hart.StallM) + if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; + else PCtextM <= #1 PCtextE; + end + + initial begin instrs = 0; end @@ -495,7 +509,7 @@ module testbench(); (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC (dut.hart.ifu.PCD == 32'h80001de0) || (dut.hart.ifu.PCD == 32'h80001de2)) begin - $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time); + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time); force CheckInstrD = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011; while (clk != 0) #1; @@ -515,10 +529,10 @@ module testbench(); $display("no more PC data to read"); `ERROR end - scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); + scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; while (PCtext2 != "***") begin - PCtext = {PCtext, " ", PCtext2}; + PCtextD = {PCtextD, " ", PCtext2}; scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); end scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); @@ -527,7 +541,7 @@ module testbench(); (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC (dut.hart.ifu.PCD == 32'h80001de0) || (dut.hart.ifu.PCD == 32'h80001de2)) begin - $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time); + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time); force CheckInstrD = 32'b0010011; force dut.hart.ifu.InstrRawD = 32'b0010011; while (clk != 0) #1; From 7d1469a06c1247a92d85e81b1dda6aa2de438cc1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 08:38:30 -0400 Subject: [PATCH 08/30] provide time and timeh CSRs based on CLINT's counter --- wally-pipelined/src/privileged/csr.sv | 1 + wally-pipelined/src/privileged/csrc.sv | 39 ++++++++++--------- wally-pipelined/src/privileged/privileged.sv | 1 + wally-pipelined/src/uncore/clint.sv | 2 +- wally-pipelined/src/uncore/uncore.sv | 3 +- .../src/wally/wallypipelinedhart.sv | 1 + .../src/wally/wallypipelinedsoc.sv | 1 + 7 files changed, 27 insertions(+), 21 deletions(-) diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index a42e29376..ae192e4dd 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -39,6 +39,7 @@ module csr #(parameter input logic InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, + input logic [63:0] MTIME, MTIMECMP, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 131338921..1fa27ea15 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -27,11 +27,11 @@ /////////////////////////////////////////// `include "wally-config.vh" - +// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes module csrc #(parameter MCYCLE = 12'hB00, -// MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT + // MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, -// MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive -// MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT + // MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + // MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -54,7 +54,7 @@ module csrc #(parameter // ... more counters //MHPMEVENT31 = 12'h33F, CYCLE = 12'hC00, -// TIME = 12'hC01, // not specified + TIME = 12'hC01, INSTRET = 12'hC02, HPMCOUNTERBASE = 12'hC00, //HPMCOUNTER3 = 12'hC03, @@ -62,7 +62,7 @@ module csrc #(parameter // ...more counters //HPMCOUNTER31 = 12'hC1F, CYCLEH = 12'hC80, -// TIMEH = 12'hC81, // not specified + TIMEH = 12'hC81, // not specified INSTRETH = 12'hC82, HPMCOUNTERHBASE = 12'hC80 //HPMCOUNTER3H = 12'hC83, @@ -71,17 +71,18 @@ module csrc #(parameter //HPMCOUNTER31H = 12'hC9F ) ( input logic clk, reset, - input logic StallD, StallE, StallM, StallW, + input logic StallD, StallE, StallM, StallW, input logic InstrValidW, LoadStallD, CSRMWriteM, - input logic BPPredDirWrongM, - input logic BTBPredPCWrongM, - input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, - input logic [4:0] InstrClassM, + input logic BPPredDirWrongM, + input logic BTBPredPCWrongM, + input logic RASPredPCWrongM, + input logic BPPredClassNonCFIWrongM, + input logic [4:0] InstrClassM, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, + input logic [63:0] MTIME, MTIMECMP, output logic [`XLEN-1:0] CSRCReadValM, output logic IllegalCSRCAccessM ); @@ -112,12 +113,12 @@ module csrc #(parameter // Counter adders with inhibits for power savings assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]}; - // assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited + //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]}; //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls - ///assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals + //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0]; - // assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0]; + //assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0]; assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0]; //assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0]; //assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0]; @@ -211,7 +212,7 @@ module csrc #(parameter //flopr #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]); end - // eventually move TIME and TIMECMP to the CLINT + // eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot! // run TIME off asynchronous reference clock // synchronize write enable to TIME // four phase handshake to synchronize reads from TIME @@ -235,7 +236,7 @@ module csrc #(parameter MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW; - // TIME: CSRCReadValM = TIME_REGW; + TIME: CSRCReadValM = MTIME; CYCLE: CSRCReadValM = CYCLE_REGW; INSTRET: CSRCReadValM = INSTRET_REGW; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -275,7 +276,7 @@ module csrc #(parameter MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; //MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32]; - // TIMEH: CSRCReadValM = TIME_REGW[63:32]; + TIMEH: CSRCReadValM = MTIME[63:32]; CYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; INSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 4f4ecd70f..839bae942 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -52,6 +52,7 @@ module privileged ( input logic LoadMisalignedFaultM, input logic StoreMisalignedFaultM, input logic TimerIntM, ExtIntM, SwIntM, + input logic [63:0] MTIME, MTIMECMP, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index df4c1e8fa..d2014468a 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -36,9 +36,9 @@ module clint ( input logic [1:0] HTRANS, output logic [`XLEN-1:0] HREADCLINT, output logic HRESPCLINT, HREADYCLINT, + output logic [63:0] MTIME, MTIMECMP, output logic TimerIntM, SwIntM); - logic [63:0] MTIMECMP, MTIME; logic MSIP; logic [15:0] entry, entryd; diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index 0eae1e611..af9f6b6b5 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -57,7 +57,8 @@ module uncore ( input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, - output logic UARTSout + output logic UARTSout, + output logic [63:0] MTIME, MTIMECMP ); logic [`XLEN-1:0] HWDATA; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 538f91546..9cc8058a5 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -34,6 +34,7 @@ module wallypipelinedhart ( input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, input logic DataAccessFaultM, + input logic [63:0] MTIME, MTIMECMP, // Bus Interface input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 7974b7ace..bde2eb2be 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -63,6 +63,7 @@ module wallypipelinedsoc ( logic [5:0] HSELRegions; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT + logic [63:0] MTIME, MTIMECMP; // from CLINT to CSRs logic ExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; From db0abfd36d47939dd042c33bf6476257d151d6c5 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 11:34:16 -0400 Subject: [PATCH 09/30] enable TIME CSR for 32 bit mode as well --- wally-pipelined/src/privileged/csrc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 1fa27ea15..006b1b72e 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -265,7 +265,7 @@ module csrc #(parameter MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - // TIME: CSRCReadValM = TIME_REGW[31:0]; + TIME: CSRCReadValM = MTIME[31:0]; CYCLE: CSRCReadValM = CYCLE_REGW[31:0]; INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; From 076469230f890f8be694d1f2cc3de9ede5216d44 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 17 Jun 2021 12:09:10 -0400 Subject: [PATCH 10/30] added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version --- wally-pipelined/src/privileged/csrc.sv | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 006b1b72e..f1cb9e0b8 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -27,11 +27,11 @@ /////////////////////////////////////////// `include "wally-config.vh" -// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes +// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking module csrc #(parameter MCYCLE = 12'hB00, - // MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT + MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, - // MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT + MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -230,8 +230,8 @@ module csrc #(parameter if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE]; else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW; + MTIMEadr: CSRCReadValM = MTIME; + MTIMECMPadr: CSRCReadValM = MTIMECMP; MCYCLE: CSRCReadValM = CYCLE_REGW; MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -259,8 +259,8 @@ module csrc #(parameter else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE]; else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW[31:0]; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW[31:0]; + MTIMEadr: CSRCReadValM = MTIME[31:0]; + MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0]; MCYCLE: CSRCReadValM = CYCLE_REGW[31:0]; MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; @@ -270,8 +270,8 @@ module csrc #(parameter INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - // MTIMEH: CSRCReadValM = TIME_REGW[63:32]; - // MTIMECMPH: CSRCReadValM = TIMECMP_REGW[63:32]; + MTIMEHadr: CSRCReadValM = MTIME[63:32]; + MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32]; MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; From 985b08c7d16eec2f3faf73b082f55bc864733793 Mon Sep 17 00:00:00 2001 From: Abe Date: Thu, 17 Jun 2021 14:49:13 -0400 Subject: [PATCH 12/30] Commit message --- riscv-coremark/coremark/core_main.c | 44 ++++++++++++++--------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/riscv-coremark/coremark/core_main.c b/riscv-coremark/coremark/core_main.c index b2149a187..edd1ac467 100644 --- a/riscv-coremark/coremark/core_main.c +++ b/riscv-coremark/coremark/core_main.c @@ -286,17 +286,17 @@ MAIN_RETURN_TYPE main(int argc, char *argv[]) { results[i].err=0; if ((results[i].execs & ID_LIST) && (results[i].crclist!=list_known_crc[known_id])) { - ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n,i,results[i].crclist,list_known_crc[known_id]"); + ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",i,results[i].crclist,list_known_crc[known_id]); results[i].err++; } if ((results[i].execs & ID_MATRIX) && (results[i].crcmatrix!=matrix_known_crc[known_id])) { - ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n,i,results[i].crcmatrix,matrix_known_crc[known_id]"); + ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",i,results[i].crcmatrix,matrix_known_crc[known_id]); results[i].err++; } if ((results[i].execs & ID_STATE) && (results[i].crcstate!=state_known_crc[known_id])) { - ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n,i,results[i].crcstate,state_known_crc[known_id]"); + ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",i,results[i].crcstate,state_known_crc[known_id]); results[i].err++; } total_errors+=results[i].err; @@ -305,55 +305,55 @@ MAIN_RETURN_TYPE main(int argc, char *argv[]) { total_errors+=check_data_types(); /* and report results */ //ee_printf("CoreMark Size : %lu\n", (long unsigned) results[0].size); - ee_printf("CoreMark Size : %lu\n, (long unsigned) results[0].size"); - ee_printf("Total ticks : %lu\n, (long unsigned) total_time"); + ee_printf("CoreMark Size : %lu\n", (long unsigned) results[0].size); + ee_printf("Total ticks : %lu\n", (long unsigned) total_time); #if HAS_FLOAT - ee_printf("Total time (secs): %f\n,time_in_secs(total_time)"); + ee_printf("Total time (secs): %f\n",time_in_secs(total_time)); if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %f\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)"); + ee_printf("Iterations/Sec : %f\n",default_num_contexts*results[0].iterations/time_in_secs(total_time)); #else ee_printf("Total time (secs): %d\n,time_in_secs(total_time)"); if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %d\n,default_num_contexts*results[0].iterations/time_in_secs(total_time)"); + ee_printf("Iterations/Sec : %d\n",default_num_contexts*results[0].iterations/time_in_secs(total_time)); #endif if (time_in_secs(total_time) < 10) { ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n"); total_errors++; } - ee_printf("Iterations : %lu\n, (long unsigned) default_num_contexts*results[0].iterations"); - ee_printf("Compiler version : %s\n,COMPILER_VERSION"); - ee_printf("Compiler flags : %s\n,COMPILER_FLAGS"); + ee_printf("Iterations : %lu\n", (long unsigned) default_num_contexts*results[0].iterations); + ee_printf("Compiler version : %s\n",COMPILER_VERSION); + ee_printf("Compiler flags : %s\n",COMPILER_FLAGS); #if (MULTITHREAD>1) - ee_printf("Parallel %s : %d\n,PARALLEL_METHOD,default_num_contexts"); + ee_printf("Parallel %s : %d\n",PARALLEL_METHOD,default_num_contexts); #endif - ee_printf("Memory location : %s\n,MEM_LOCATION"); + ee_printf("Memory location : %s\n",MEM_LOCATION); /* output for verification */ - ee_printf("seedcrc : 0x%04x\n,seedcrc"); + ee_printf("seedcrc : 0x%04x\n",seedcrc); if (results[0].execs & ID_LIST) for (i=0 ; i1) - ee_printf(" / %d:%s,default_num_contexts,PARALLEL_METHOD"); + ee_printf(" / %d:%s",default_num_contexts,PARALLEL_METHOD); #endif ee_printf("\n"); } From 09c5e27853a35f8e16f4cc508ae1d356ed32f073 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 17 Jun 2021 16:28:06 -0400 Subject: [PATCH 13/30] Started simplifying PMA checker --- wally-pipelined/config/rv32ic/wally-config.vh | 8 ++ wally-pipelined/config/rv64ic/wally-config.vh | 6 ++ wally-pipelined/src/mmu/pmaadrdec.sv | 45 +++++++++++ wally-pipelined/src/mmu/pmachecker.sv | 76 +++++++------------ 4 files changed, 85 insertions(+), 50 deletions(-) create mode 100644 wally-pipelined/src/mmu/pmaadrdec.sv diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 7bbe713a6..6f17e2591 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -61,16 +61,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 1c94adf02..d9928cdb6 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -65,18 +65,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF //`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder //`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv new file mode 100644 index 000000000..ea7688a2b --- /dev/null +++ b/wally-pipelined/src/mmu/pmaadrdec.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// pmaadrdec.sv +// +// Written: David_Harris@hmc.edu 29 January 2021 +// Modified: +// +// Purpose: Address decoder +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module pmaadrdec ( + input logic [31:0] HADDR, + input logic [31:0] Base, Range, + input logic Supported, + output logic HSEL +); + + logic [31:0] match; + + // determine if an address is in a range starting at the base + // for example, if Base = 0x04002000 and range = 0x00000FFF, + // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1) + + assign match = (HADDR ~^ Base) | Range; + assign HSEL = &match & Supported; + +endmodule + diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 61c02426c..f188bb27a 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -54,15 +54,30 @@ module pmachecker ( logic HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC; logic ValidBootTim, ValidTim, ValidCLINT, ValidGPIO, ValidUART, ValidPLIC; - // Attributes of memory region accessed - logic Executable, Readable, Writable; + logic PMAAccessFault; + logic AccessRW, AccessRWX, AccessRX; - logic Fault; + // Determine what type of access is being made + assign AccessRW = ReadAccessM | WriteAccessM; + assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF; + assign AccessRX = ReadAccessM | ExecuteAccessF; - attributes attributes(.Address(HADDR), .*); - // Unswizzle region bits - assign {BootTim, Tim, CLINT, GPIO, UART, PLIC} = Regions; + // Determine which region of physical memory (if any) is being accessed + pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, BootTim); + pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, Tim); + pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, CLINT); + pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, GPIO); + pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, UART); + pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, PLIC); + + // Swizzle region bits + assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; + + // Only RAM memory regions are cacheable + assign Cacheable = BootTim | Tim; + assign Idempotent = BootTim | Tim; + assign AtomicAllowed = BootTim | Tim; assign ValidBootTim = '1; assign ValidTim = '1; @@ -81,50 +96,11 @@ module pmachecker ( // Swizzle region bits assign HSELRegions = {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC}; - assign Fault = ~|HSELRegions; + assign PMAAccessFault = ~|HSELRegions; - assign PMAInstrAccessFaultF = ExecuteAccessF && Fault; - assign PMALoadAccessFaultM = ReadAccessM && Fault; - assign PMAStoreAccessFaultM = WriteAccessM && Fault; - - assign PMASquashBusAccess = PMAInstrAccessFaultF || PMALoadAccessFaultM || PMAStoreAccessFaultM; - -endmodule - -module attributes ( -// input logic clk, reset, // *** unused in this module and all sub modules. - - input logic [31:0] Address, - - output logic [5:0] Regions, - - output logic Cacheable, Idempotent, AtomicAllowed, - output logic Executable, Readable, Writable -); - - // Signals are high if the memory access is within the given region - logic BootTim, Tim, CLINT, GPIO, UART, PLIC; - - // Determine which region of physical memory (if any) is being accessed - adrdec boottimdec(Address, `BOOTTIMBASE, `BOOTTIMRANGE, BootTim); - adrdec timdec(Address, `TIMBASE, `TIMRANGE, Tim); - adrdec clintdec(Address, `CLINTBASE, `CLINTRANGE, CLINT); - adrdec gpiodec(Address, `GPIOBASE, `GPIORANGE, GPIO); - adrdec uartdec(Address, `UARTBASE, `UARTRANGE, UART); - adrdec plicdec(Address, `PLICBASE, `PLICRANGE, PLIC); - - // Swizzle region bits - assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; - - // Only RAM memory regions are cacheable - assign Cacheable = BootTim | Tim; - - assign Idempotent = BootTim | Tim; - - assign AtomicAllowed = BootTim | Tim; - - assign Executable = BootTim | Tim; - assign Readable = BootTim | Tim | CLINT | GPIO | UART | PLIC; - assign Writable = BootTim | Tim | CLINT | GPIO | UART | PLIC; + assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; + assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; + assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; + assign PMASquashBusAccess = PMAAccessFault && AccessRWX; endmodule From 5e7ed4bd8805c2d95b2f583edc0babb4b06a6e08 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 17 Jun 2021 18:54:39 -0400 Subject: [PATCH 14/30] added inputs to pmaadrdec --- wally-pipelined/src/mmu/pmaadrdec.sv | 7 +++++-- wally-pipelined/src/mmu/pmachecker.sv | 18 +++++++++--------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv index ea7688a2b..bc2178764 100644 --- a/wally-pipelined/src/mmu/pmaadrdec.sv +++ b/wally-pipelined/src/mmu/pmaadrdec.sv @@ -29,6 +29,9 @@ module pmaadrdec ( input logic [31:0] HADDR, input logic [31:0] Base, Range, input logic Supported, + input logic AccessValid, + input logic [2:0] Size, + input logic [3:0] SizeMask, output logic HSEL ); @@ -38,8 +41,8 @@ module pmaadrdec ( // for example, if Base = 0x04002000 and range = 0x00000FFF, // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1) - assign match = (HADDR ~^ Base) | Range; - assign HSEL = &match & Supported; + assign match = &((HADDR ~^ Base) | Range); + assign HSEL = match & Supported; endmodule diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index f188bb27a..95a821799 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -64,20 +64,20 @@ module pmachecker ( // Determine which region of physical memory (if any) is being accessed - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, BootTim); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, Tim); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, CLINT); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, GPIO); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, UART); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, PLIC); + pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, Size, 4'b1111, BootTim); + pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, Size, 4'b1111, Tim); + pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, Size, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT); + pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, Size, 4'b0100, GPIO); + pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, Size, 4'b0001, UART); + pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, Size, 4'b0100, PLIC); // Swizzle region bits assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; // Only RAM memory regions are cacheable assign Cacheable = BootTim | Tim; - assign Idempotent = BootTim | Tim; - assign AtomicAllowed = BootTim | Tim; + assign Idempotent = Tim; + assign AtomicAllowed = Tim; assign ValidBootTim = '1; assign ValidTim = '1; @@ -98,9 +98,9 @@ module pmachecker ( assign PMAAccessFault = ~|HSELRegions; + // Detect access faults assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; - assign PMASquashBusAccess = PMAAccessFault && AccessRWX; endmodule From 91a13999a94e12bcba2bf8fb844cffad1fee7aaf Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 17 Jun 2021 21:36:32 -0400 Subject: [PATCH 15/30] Added SUPPORTED to each peripheral in each config file --- .../config/buildroot/wally-config.vh | 31 +++++++++++-------- .../config/busybear/wally-config.vh | 28 ++++++++++------- .../config/coremark-64i/wally-config.vh | 16 ++++++++-- .../config/coremark/wally-config.vh | 12 +++++-- .../config/coremark_bare/wally-config.vh | 12 +++++-- wally-pipelined/config/rv64BP/wally-config.vh | 10 +++++- .../config/rv64icfd/wally-config.vh | 15 ++++++--- .../config/rv64imc/wally-config.vh | 12 +++++-- wally-pipelined/src/mmu/pmaadrdec.sv | 2 +- wally-pipelined/src/mmu/pmachecker.sv | 12 +++---- 10 files changed, 106 insertions(+), 44 deletions(-) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 826f560f6..065a6ebc1 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -1,5 +1,5 @@ ////////////////////////////////////////// -// busybear-config.vh +// wally-config.vh // // Written: David_Harris@hmc.edu 4 January 2021 // Modified: @@ -61,22 +61,27 @@ // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define VBD0BASE 32'h10001000 -`define VBD0RANGE 32'h000001FF -// differing from Imperas' OVPSim by not having a VND0 -`define GPIOBASE 32'h20000000 -`define GPIORANGE 32'h000000FF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF + // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index ce189ff1a..da7db2288 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -62,21 +62,27 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define VBD0BASE 32'h10001000 -`define VBD0RANGE 32'h000001FF -// differing from Imperas' OVPSim by not having a VND0 -`define GPIOBASE 32'h20000000 -`define GPIORANGE 32'h000000FF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF + // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh index 2ac36a2a7..848cb3bc4 100644 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ b/wally-pipelined/config/coremark-64i/wally-config.vh @@ -54,14 +54,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define BOOTTIMSUPPORTED 1'b1 +`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIMRANGE 32'h00003FFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index d5935665e..615e18024 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -62,16 +62,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h00000000 -`define TIMRANGE 32'hFFFFFFFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 2a9a6c4cb..219e42253 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -62,16 +62,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h000FFFFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 6cc8ce732..0cf38f28e 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -63,16 +63,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h00000000 +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 0b0726beb..20da468c4 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -65,17 +65,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMSUPPORTED 1'b1 +`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h80000000 -// `define TIMRANGE 32'h0007FFFF -`define TIMRANGE 32'h07FFFFFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index be0970dee..5e63f6dae 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -61,16 +61,24 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMSUPPORTED 1'b1 `define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIMRANGE 32'h00000FFF +`define TIMSUPPORTED 1'b1 +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF +`define CLINTSUPPORTED 1'b1 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF +`define GPIOSUPPORTED 1'b1 `define GPIOBASE 32'h10012000 `define GPIORANGE 32'h000000FF +`define UARTSUPPORTED 1'b1 `define UARTBASE 32'h10000000 `define UARTRANGE 32'h00000007 +`define PLICSUPPORTED 1'b1 `define PLICBASE 32'h0C000000 `define PLICRANGE 32'h03FFFFFF diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv index bc2178764..a133503b7 100644 --- a/wally-pipelined/src/mmu/pmaadrdec.sv +++ b/wally-pipelined/src/mmu/pmaadrdec.sv @@ -35,7 +35,7 @@ module pmaadrdec ( output logic HSEL ); - logic [31:0] match; + logic match; // determine if an address is in a range starting at the base // for example, if Base = 0x04002000 and range = 0x00000FFF, diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 95a821799..8821c0cfb 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -64,12 +64,12 @@ module pmachecker ( // Determine which region of physical memory (if any) is being accessed - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, Size, 4'b1111, BootTim); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, Size, 4'b1111, Tim); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, Size, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, Size, 4'b0100, GPIO); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, Size, 4'b0001, UART); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, Size, 4'b0100, PLIC); + pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, HSIZE, 4'b1111, BootTim); + pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, HSIZE, 4'b1111, Tim); + pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT); + pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, GPIO); + pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, UART); + pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, PLIC); // Swizzle region bits assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; From 8357b1495769a42109ca8d4cfc9a0dae7897fa6a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 17 Jun 2021 22:27:39 -0400 Subject: [PATCH 16/30] Further cleaning of PMA checker --- wally-pipelined/src/mmu/pmaadrdec.sv | 10 ++++-- wally-pipelined/src/mmu/pmachecker.sv | 51 ++++++++------------------- 2 files changed, 21 insertions(+), 40 deletions(-) diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv index a133503b7..c48cdc665 100644 --- a/wally-pipelined/src/mmu/pmaadrdec.sv +++ b/wally-pipelined/src/mmu/pmaadrdec.sv @@ -35,14 +35,18 @@ module pmaadrdec ( output logic HSEL ); - logic match; + logic Match; + logic SizeValid; // determine if an address is in a range starting at the base // for example, if Base = 0x04002000 and range = 0x00000FFF, // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1) + assign Match = &((HADDR ~^ Base) | Range); - assign match = &((HADDR ~^ Base) | Range); - assign HSEL = match & Supported; + // determine if legal size of access is being made (byte, halfword, word, doubleword) + assign SizeValid = SizeMask[Size[1:0]]; + + assign HSEL = Match && Supported && AccessValid && SizeValid; endmodule diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 8821c0cfb..b8ecc366a 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -46,14 +46,7 @@ module pmachecker ( output logic PMAStoreAccessFaultM ); - // Signals are high if the memory access is within the given region - logic BootTim, Tim, CLINT, GPIO, UART, PLIC; - logic [5:0] Regions; - - // Actual HSEL signals sent to uncore - logic HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC; - logic ValidBootTim, ValidTim, ValidCLINT, ValidGPIO, ValidUART, ValidPLIC; - + // logic BootTim, Tim, CLINT, GPIO, UART, PLIC; logic PMAAccessFault; logic AccessRW, AccessRWX, AccessRX; @@ -62,43 +55,27 @@ module pmachecker ( assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF; assign AccessRX = ReadAccessM | ExecuteAccessF; - // Determine which region of physical memory (if any) is being accessed - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, HSIZE, 4'b1111, BootTim); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, HSIZE, 4'b1111, Tim); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, GPIO); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, UART); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, PLIC); - - // Swizzle region bits - assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; + // *** linux tests fail early when Access is anything other than 1b1 + pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); + pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); + pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), HSELRegions[3]); + pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); + pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); + pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); // Only RAM memory regions are cacheable - assign Cacheable = BootTim | Tim; - assign Idempotent = Tim; - assign AtomicAllowed = Tim; + assign Cacheable = HSELRegions[5] | HSELRegions[4]; + assign Idempotent = HSELRegions[4]; + assign AtomicAllowed = HSELRegions[4]; - assign ValidBootTim = '1; - assign ValidTim = '1; - assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011 && `XLEN==64) || (HSIZE == 3'b010 && `XLEN==32)); - assign ValidGPIO = ~ExecuteAccessF && (HSIZE == 3'b010); - assign ValidUART = ~ExecuteAccessF && (HSIZE == 3'b000); - assign ValidPLIC = ~ExecuteAccessF && (HSIZE == 3'b010); - - assign HSELBootTim = BootTim && ValidBootTim; - assign HSELTim = Tim && ValidTim; - assign HSELCLINT = CLINT && ValidCLINT; - assign HSELGPIO = GPIO && ValidGPIO; - assign HSELUART = UART && ValidUART; // only byte writes to UART are supported - assign HSELPLIC = PLIC && ValidPLIC; + /*ExecuteAccessF | ReadAccessM | WriteAccessM; */ // Swizzle region bits - assign HSELRegions = {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC}; - - assign PMAAccessFault = ~|HSELRegions; + //assign HSELRegions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; // Detect access faults + assign PMAAccessFault = ~|HSELRegions; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; From e03912f64c2a81cd85a0d7e2318d7ca016a37c19 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 07:53:49 -0400 Subject: [PATCH 17/30] Cleaned up name of MTIME register in CSRC --- .../regression/vsim_stacktrace.vstf | 1534 +++++++++++++++++ wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrc.sv | 28 +- wally-pipelined/src/privileged/privileged.sv | 2 +- wally-pipelined/src/uncore/uncore.sv | 15 +- .../src/wally/wallypipelinedhart.sv | 2 +- .../src/wally/wallypipelinedsoc.sv | 2 +- .../testbench/testbench-busybear.sv | 5 + wally-pipelined/testbench/testbench-linux.sv | 10 + 10 files changed, 1570 insertions(+), 32 deletions(-) create mode 100644 wally-pipelined/regression/vsim_stacktrace.vstf diff --git a/wally-pipelined/regression/vsim_stacktrace.vstf b/wally-pipelined/regression/vsim_stacktrace.vstf new file mode 100644 index 000000000..e524b9173 --- /dev/null +++ b/wally-pipelined/regression/vsim_stacktrace.vstf @@ -0,0 +1,1534 @@ +# Current time Thu Jun 17 21:48:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c6549: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:48:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:50:07 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c6549: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 21:50:07 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:04:29 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x00000000027777ef: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x0000000000f5be1c: '' +# 6 0x0000000000b98fd0: '' +# 7 0x0000000000b9923c: '' +# 8 0x0000000000b9b3f0: '' +# 9 0x000000000057f81c: '' +# 10 0x00000000006e7153: '' +# 11 0x0000000000c01b55: '' +# 12 0x0000000000c069ab: '' +# 13 0x0000000000c0828e: '' +# 14 0x0000000000ebfecd: '' +# 15 0x0000000002bdcfdd: '' +# 16 0x0000000002be1436: '' +# 17 0x0000000002be2b21: '' +# 18 0x0000000002be2e86: '' +# 19 0x0000000001125d89: '' +# 20 0x0000000002c82d8f: '' +# 21 0x0000000002cd6907: '' +# 22 0x0000000002c997f7: '' +# 23 0x0000000002c99ad9: '' +# 24 0x0000000002a9bfdd: '' +# 25 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:29:27 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:29:27 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:32:57 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:32:57 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:41:45 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:41:45 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:42:25 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:42:25 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:49:19 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5cf9: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Thu Jun 17 22:49:19 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 01:12:23 2021 +# Program = vsim +# Id = "2021.2_1" +# Version = "2021.05" +# Date = "May 15 2021" +# Platform = "linux_x86_64" +# Signature = dfcd0de65e8129bcb66fdbdef15ad702 +# 0 0x0000000003466f2d: '' +# 1 0x0000000000fc45c0: '' +# 2 0x00000000010f3e57: '' +# 3 0x00000000010f3f1e: '' +# 4 0x00000000010f406b: '' +# 5 0x00000000010f4ee4: '' +# 6 0x0000000000610603: '' +# 7 0x000000000061e1e6: '' +# 8 0x00007feff0365c5a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000345ecda: '' +# 10 0x00000000004c6e84: '' +# 11 0x00000000006e8203: '' +# 12 0x0000000000c03175: '' +# 13 0x0000000000c08033: '' +# 14 0x0000000000c09d8e: '' +# 15 0x0000000000ed3f8d: '' +# 16 0x00000000038ee98d: '' +# 17 0x00000000038f2de6: '' +# 18 0x00000000038f44d1: '' +# 19 0x00000000038f4836: '' +# 20 0x0000000001145ab9: '' +# 21 0x000000000399473f: '' +# 22 0x00000000039e82b7: '' +# 23 0x00000000039ab1a7: '' +# 24 0x00000000039ab489: '' +# 25 0x0000000003790c2d: '' +# 26 0x0000000000bcf05c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 01:12:23 2021 +# Program = vsim +# Id = "2021.2_1" +# Version = "2021.05" +# Date = "May 15 2021" +# Platform = "linux_x86_64" +# Signature = dfcd0de65e8129bcb66fdbdef15ad702 +# 0 0x0000000003466f2d: '' +# 1 0x00000000034671a6: '' +# 2 0x0000000000753790: '' +# 3 0x000000000347e9d9: '' +# 4 0x0000000000753862: '' +# 5 0x00000000006a853d: '' +# 6 0x0000000000f63259: '' +# 7 0x0000000000c02e65: '' +# 8 0x0000000000c037ba: '' +# 9 0x0000000000c08033: '' +# 10 0x0000000000c09d8e: '' +# 11 0x0000000000ed3f8d: '' +# 12 0x00000000038ee98d: '' +# 13 0x00000000038f2de6: '' +# 14 0x00000000038f44d1: '' +# 15 0x00000000038f4836: '' +# 16 0x0000000001145ab9: '' +# 17 0x000000000399473f: '' +# 18 0x00000000039e82b7: '' +# 19 0x00000000039ab1a7: '' +# 20 0x00000000039ab489: '' +# 21 0x0000000003790c2d: '' +# 22 0x0000000000bcf05c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:14:05 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007feff06c5d19: '../testbench/testbench-linux.sv:536' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:14:05 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:17:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:17:46 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:19:28 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:19:28 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:21:11 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:21:11 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:22:31 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:22:31 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:24:04 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:536' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:24:04 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:37:14 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a00a: '../testbench/testbench-linux.sv:537' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:37:14 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:39:03 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a01a: '../testbench/testbench-linux.sv:538' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:39:03 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:40:53 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a04a: '../testbench/testbench-linux.sv:541' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:40:53 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:42:30 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:42:30 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:43:39 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:43:39 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:44:37 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d8b44: '' +# 4 0x00000000010d8bac: '' +# 5 0x00000000010cef65: '' +# 6 0x00000000010d12f0: '' +# 7 0x00000000010d4700: '' +# 8 0x00000000007cded8: '' +# 9 0x0000000000809da8: '' +# 10 0x000000000081d399: '' +# 11 0x00000000007cb83e: '' +# 12 0x00007fefec49a035: '../testbench/testbench-linux.sv:543' +# 13 0x000000000276f58a: '' +# 14 0x0000000000554abb: '' +# 15 0x00000000006e7153: '' +# 16 0x0000000000c01b55: '' +# 17 0x0000000000c069ab: '' +# 18 0x0000000000c0828e: '' +# 19 0x0000000000ebfecd: '' +# 20 0x0000000002bdcfdd: '' +# 21 0x0000000002be1436: '' +# 22 0x0000000002be2b21: '' +# 23 0x0000000002be2e86: '' +# 24 0x0000000001125d89: '' +# 25 0x0000000002c82d8f: '' +# 26 0x0000000002cd6907: '' +# 27 0x0000000002c997f7: '' +# 28 0x0000000002c99ad9: '' +# 29 0x0000000002a9bfdd: '' +# 30 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:44:37 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:47:43 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x0000000000fac730: '' +# 2 0x00000000010d8667: '' +# 3 0x00000000010d872e: '' +# 4 0x00000000010d887b: '' +# 5 0x00000000010d96f4: '' +# 6 0x000000000061ce93: '' +# 7 0x000000000062a516: '' +# 8 0x00007fefec49a059: '../testbench/testbench-linux.sv:542' +# 9 0x000000000276f58a: '' +# 10 0x0000000000554abb: '' +# 11 0x00000000006e7153: '' +# 12 0x0000000000c01b55: '' +# 13 0x0000000000c069ab: '' +# 14 0x0000000000c0828e: '' +# 15 0x0000000000ebfecd: '' +# 16 0x0000000002bdcfdd: '' +# 17 0x0000000002be1436: '' +# 18 0x0000000002be2b21: '' +# 19 0x0000000002be2e86: '' +# 20 0x0000000001125d89: '' +# 21 0x0000000002c82d8f: '' +# 22 0x0000000002cd6907: '' +# 23 0x0000000002c997f7: '' +# 24 0x0000000002c99ad9: '' +# 25 0x0000000002a9bfdd: '' +# 26 0x0000000000bcf27c: '' +# End of Stack Trace + + +# Current time Fri Jun 18 07:47:43 2021 +# Program = vsim +# Id = "2020.4_2" +# Version = "2020.12" +# Date = "Dec 5 2020" +# Platform = "linux_x86_64" +# Signature = 3855e86be6633fb934af752a2c9bf4ab +# 0 0x000000000277775d: '' +# 1 0x00000000027779d6: '' +# 2 0x000000000074f9d0: '' +# 3 0x000000000278ed16: '' +# 4 0x000000000074fd69: '' +# 5 0x00000000006abc9d: '' +# 6 0x0000000000f4c589: '' +# 7 0x0000000000c01845: '' +# 8 0x0000000000c0219a: '' +# 9 0x0000000000c069ab: '' +# 10 0x0000000000c0828e: '' +# 11 0x0000000000ebfecd: '' +# 12 0x0000000002bdcfdd: '' +# 13 0x0000000002be1436: '' +# 14 0x0000000002be2b21: '' +# 15 0x0000000002be2e86: '' +# 16 0x0000000001125d89: '' +# 17 0x0000000002c82d8f: '' +# 18 0x0000000002cd6907: '' +# 19 0x0000000002c997f7: '' +# 20 0x0000000002c99ad9: '' +# 21 0x0000000002a9bfdd: '' +# 22 0x0000000000bcf27c: '' +# End of Stack Trace + + diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 11876dded..0be7fcdd9 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -do ./wave-dos/linux-waves.do +#do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index ae192e4dd..d29104fc7 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -39,7 +39,7 @@ module csr #(parameter input logic InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index f1cb9e0b8..c762ea8c3 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -30,8 +30,8 @@ // Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking module csrc #(parameter MCYCLE = 12'hB00, - MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT + MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, - MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT + MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -82,7 +82,7 @@ module csrc #(parameter input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, output logic [`XLEN-1:0] CSRCReadValM, output logic IllegalCSRCAccessM ); @@ -230,13 +230,13 @@ module csrc #(parameter if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE]; else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE]; else case (CSRAdrM) - MTIMEadr: CSRCReadValM = MTIME; - MTIMECMPadr: CSRCReadValM = MTIMECMP; + MTIME: CSRCReadValM = MTIME_CLINT; + MTIMECMP: CSRCReadValM = MTIMECMP_CLINT; MCYCLE: CSRCReadValM = CYCLE_REGW; MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW; - TIME: CSRCReadValM = MTIME; + TIME: CSRCReadValM = MTIME_CLINT; CYCLE: CSRCReadValM = CYCLE_REGW; INSTRET: CSRCReadValM = INSTRET_REGW; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -259,24 +259,24 @@ module csrc #(parameter else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE]; else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE]; else case (CSRAdrM) - MTIMEadr: CSRCReadValM = MTIME[31:0]; - MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0]; + MTIME: CSRCReadValM = MTIME_CLINT[31:0]; + MTIMECMP: CSRCReadValM = MTIMECMP_CLINT[31:0]; MCYCLE: CSRCReadValM = CYCLE_REGW[31:0]; MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - TIME: CSRCReadValM = MTIME[31:0]; + TIME: CSRCReadValM = MTIME_CLINT[31:0]; CYCLE: CSRCReadValM = CYCLE_REGW[31:0]; INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - MTIMEHadr: CSRCReadValM = MTIME[63:32]; - MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32]; + MTIMEH: CSRCReadValM = MTIME_CLINT[63:32]; + MTIMECMPH: CSRCReadValM = MTIMECMP_CLINT[63:32]; MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; //MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32]; - TIMEH: CSRCReadValM = MTIME[63:32]; + TIMEH: CSRCReadValM = MTIME_CLINT[63:32]; CYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; INSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32]; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 839bae942..061b6a37c 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -52,7 +52,7 @@ module privileged ( input logic LoadMisalignedFaultM, input logic StoreMisalignedFaultM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index af9f6b6b5..fb8483768 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -58,7 +58,7 @@ module uncore ( output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, output logic UARTSout, - output logic [63:0] MTIME, MTIMECMP + output logic [63:0] MTIME_CLINT, MTIMECMP_CLINT ); logic [`XLEN-1:0] HWDATA; @@ -76,17 +76,6 @@ module uncore ( // unswizzle HSEL signals assign {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC} = HSELRegions; - /* PMA checker now handles decoding addresses. *** This can be deleted. - // AHB Address decoder - adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim); - adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim); - adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT); - adrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, HSELPLIC); - adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); - adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART); - assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported - */ - // subword accesses: converts HWDATAIN to HWDATA subwordwrite sww(.*); @@ -95,7 +84,7 @@ module uncore ( dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); // memory-mapped I/O peripherals - clint clint(.HADDR(HADDR[15:0]), .*); + clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); plic plic(.HADDR(HADDR[27:0]), .*); gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9cc8058a5..2535eef3d 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -34,7 +34,7 @@ module wallypipelinedhart ( input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, input logic DataAccessFaultM, - input logic [63:0] MTIME, MTIMECMP, + input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, // Bus Interface input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index bde2eb2be..c85f5d4f4 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -63,7 +63,7 @@ module wallypipelinedsoc ( logic [5:0] HSELRegions; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT - logic [63:0] MTIME, MTIMECMP; // from CLINT to CSRs + logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs logic ExtIntM; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 0ca22608e..c3c84de2e 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -493,7 +493,12 @@ module testbench(); end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); PCtext2 = ""; + $display("loading tests"); + $display("PCtext = %s\n", PCtext); while (PCtext2 != "***") begin + $display("debugging\n"); + $display("PCtext is %s\n", PCtext); + $display("PCtext %s PCtext2 %s\n", PCtext, PCtext2); PCtext = {PCtext, " ", PCtext2}; scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); end diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 6cf20e674..9f80a33d4 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -494,11 +494,14 @@ module testbench(); logic [31:0] InstrMask; logic forcedInstr; logic [63:0] lastPCD; + always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin if(~HWRITE) begin #2; + $display("test point"); if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin if (dut.hart.ifu.PCD !== lastPCD) begin + $display("tp2"); lastCheckInstrD = CheckInstrD; lastPC <= dut.hart.ifu.PCD; lastPC2 <= lastPC; @@ -525,16 +528,22 @@ module testbench(); end end else begin + $display("tp4"); if($feof(data_file_PC)) begin $display("no more PC data to read"); `ERROR end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; + $display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); while (PCtext2 != "***") begin + $display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); PCtextD = {PCtextD, " ", PCtext2}; + $display("tp8"); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); + $display("tp9"); end + $display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); if(dut.hart.ifu.PCD === pcExpected) begin if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs @@ -607,6 +616,7 @@ module testbench(); end end + // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; From 72d8d34e3c6d94f64035e41674157428b959e648 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 08:05:50 -0400 Subject: [PATCH 18/30] allow all size memory access in CLINT; added underscore to peripheral address symbols --- .../config/buildroot/wally-config.vh | 40 +++++++++---------- .../config/busybear/wally-config.vh | 40 +++++++++---------- .../config/coremark-64i/wally-config.vh | 40 +++++++++---------- .../config/coremark/wally-config.vh | 40 +++++++++---------- .../config/coremark_bare/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv32ic/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv64BP/wally-config.vh | 40 +++++++++---------- wally-pipelined/config/rv64ic/wally-config.vh | 40 +++++++++---------- .../config/rv64icfd/wally-config.vh | 40 +++++++++---------- .../config/rv64imc/wally-config.vh | 40 +++++++++---------- wally-pipelined/src/mmu/pmachecker.sv | 17 +++----- wally-pipelined/src/uncore/imem.sv | 16 ++++---- wally-pipelined/src/uncore/uncore.sv | 4 +- .../testbench/testbench-imperas.sv | 8 ++-- .../testbench/testbench-privileged.sv | 4 +- 15 files changed, 222 insertions(+), 227 deletions(-) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 065a6ebc1..c5469e357 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index da7db2288..516ebcae7 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 64 diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh index 848cb3bc4..f72b4f616 100644 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ b/wally-pipelined/config/coremark-64i/wally-config.vh @@ -54,26 +54,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 615e18024..13d364dd7 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 219e42253..5b62a23e0 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -62,26 +62,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 6f17e2591..f6f1860ad 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Bus Interface width `define AHBW 32 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 0cf38f28e..477055def 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -63,26 +63,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index d9928cdb6..32943165e 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -65,26 +65,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 20da468c4..1a7df3c40 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -65,26 +65,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index 5e63f6dae..b6f5ab9af 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -61,26 +61,26 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTTIMSUPPORTED 1'b1 -`define BOOTTIMBASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTTIMRANGE 32'h00003FFF -//`define BOOTTIMBASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTTIMRANGE 32'h00000FFF -`define TIMSUPPORTED 1'b1 -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h07FFFFFF -`define CLINTSUPPORTED 1'b1 -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOSUPPORTED 1'b1 -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTSUPPORTED 1'b1 -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICSUPPORTED 1'b1 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define BOOTTIM_SUPPORTED 1'b1 +`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTTIM_RANGE 32'h00003FFF +//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +//`define BOOTTIM_RANGE 32'h00000FFF +`define TIM_SUPPORTED 1'b1 +`define TIM_BASE 32'h80000000 +`define TIM_RANGE 32'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 32'h02000000 +`define CLINT_RANGE 32'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 32'h10012000 +`define GPIO_RANGE 32'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 32'h10000000 +`define UART_RANGE 32'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 32'h0C000000 +`define PLIC_RANGE 32'h03FFFFFF // Test modes diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index b8ecc366a..0aaa8b976 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -57,23 +57,18 @@ module pmachecker ( // Determine which region of physical memory (if any) is being accessed // *** linux tests fail early when Access is anything other than 1b1 - pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); - pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); - pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, HSIZE, (`XLEN==64 ? 4'b1000 : 4'b0100), HSELRegions[3]); - pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); - pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); - pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); + pmaadrdec boottimdec(HADDR, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]); + pmaadrdec timdec(HADDR, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]); + pmaadrdec clintdec(HADDR, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, HSIZE, 4'b1111, HSELRegions[3]); + pmaadrdec gpiodec(HADDR, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]); + pmaadrdec uartdec(HADDR, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]); + pmaadrdec plicdec(HADDR, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]); // Only RAM memory regions are cacheable assign Cacheable = HSELRegions[5] | HSELRegions[4]; assign Idempotent = HSELRegions[4]; assign AtomicAllowed = HSELRegions[4]; - /*ExecuteAccessF | ReadAccessM | WriteAccessM; */ - - // Swizzle region bits - //assign HSELRegions = {BootTim, Tim, CLINT, GPIO, UART, PLIC}; - // Detect access faults assign PMAAccessFault = ~|HSELRegions; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 6aaad5982..85362edf7 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -32,8 +32,8 @@ module imem ( output logic InstrAccessFaultF); /* verilator lint_off UNDRIVEN */ - logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)]; - logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)]; + logic [`XLEN-1:0] RAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>(1+`XLEN/32)]; + logic [`XLEN-1:0] bootram[`BOOTTIM_BASE>>(1+`XLEN/32):(`BOOTTIM_RANGE+`BOOTTIM_BASE)>>(1+`XLEN/32)]; /* verilator lint_on UNDRIVEN */ logic [31:0] adrbits; // needs to be 32 bits to index RAM logic [`XLEN-1:0] rd; @@ -44,27 +44,27 @@ module imem ( else assign adrbits = AdrF[31:3]; endgenerate - assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options + assign #2 rd = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options // hack right now for unaligned 32-bit instructions // eventually this will need to cause a stall like a cache miss // when the instruction wraps around a cache line // could be optimized to only stall when the instruction wrapping is 32 bits - assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options + assign #2 rd2 = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options generate if (`XLEN==32) begin assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd; // First, AdrF needs to get its last bit appended back onto it - // Then not-XORing it with TIMBASE checks if it matches TIMBASE exactly - // Then ORing it with TIMRANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low + // Then not-XORing it with TIM_BASE checks if it matches TIM_BASE exactly + // Then ORing it with TIM_RANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low - assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIMBASE) | `TIMRANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIMBASE) | `BOOTTIMRANGE)); + assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIM_BASE) | `TIM_RANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIM_BASE) | `BOOTTIM_RANGE)); end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); // - assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIMBASE | `BOOTTIMRANGE)); + assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIM_BASE | `TIM_RANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIM_BASE | `BOOTTIM_RANGE)); end endgenerate endmodule diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index fb8483768..d49414a79 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -80,8 +80,8 @@ module uncore ( subwordwrite sww(.*); // tightly integrated memory - dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*); - dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); + dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*); + dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); // memory-mapped I/O peripherals clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index e67606ec1..f87f369b4 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -582,8 +582,8 @@ string tests32f[] = '{ InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests - localparam integer MemStartAddr = `TIMBASE>>(1+`XLEN/32); - localparam integer MemEndAddr = (`TIMRANGE+`TIMBASE)>>1+(`XLEN/32); + localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32); + localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32); initial begin @@ -655,9 +655,9 @@ string tests32f[] = '{ errors = (i == SIGNATURESIZE+1); // error if file is empty i = 0; if (`XLEN == 32) - testadr = (`TIMBASE+tests[test+1].atohex())/4; + testadr = (`TIM_BASE+tests[test+1].atohex())/4; else - testadr = (`TIMBASE+tests[test+1].atohex())/8; + testadr = (`TIM_BASE+tests[test+1].atohex())/8; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin //$display("signature[%h] = %h", i, signature[i]); diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index a10959b3e..c3e8e20f1 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -159,9 +159,9 @@ module testbench(); i = 0; errors = 0; if (`XLEN == 32) - testadr = (`TIMBASE+tests[test+1].atohex())/4; + testadr = (`TIM_BASE+tests[test+1].atohex())/4; else - testadr = (`TIMBASE+tests[test+1].atohex())/8; + testadr = (`TIM_BASE+tests[test+1].atohex())/8; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin //$display("signature[%h] = %h", i, signature[i]); From cc78504ae4c2bf6b38d54c9397e96bac7dcf2f29 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 08:13:15 -0400 Subject: [PATCH 19/30] Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX --- wally-pipelined/src/mmu/pmachecker.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 0aaa8b976..703bb81b2 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -70,9 +70,9 @@ module pmachecker ( assign AtomicAllowed = HSELRegions[4]; // Detect access faults - assign PMAAccessFault = ~|HSELRegions; + assign PMAAccessFault = (~|HSELRegions) && AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; - assign PMASquashBusAccess = PMAAccessFault && AccessRWX; + assign PMASquashBusAccess = PMAAccessFault; endmodule From 8ae333a6b2e92ad5d80472885d1bd520096f66c6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 08:15:19 -0400 Subject: [PATCH 20/30] remove unused testbench-busybear.sv --- .../testbench/testbench-busybear.sv | 716 ------------------ 1 file changed, 716 deletions(-) delete mode 100644 wally-pipelined/testbench/testbench-busybear.sv diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv deleted file mode 100644 index c3c84de2e..000000000 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ /dev/null @@ -1,716 +0,0 @@ -`include "wally-config.vh" - - -module testbench(); - logic clk, reset; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; - - // instantiate device to be tested - logic [31:0] CheckInstrD; - - logic [`AHBW-1:0] HRDATA; - logic [31:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic UARTSout; - - assign GPIOPinsIn = 0; - assign UARTSin = 1; - - // instantiate processor and memories - wallypipelinedsoc dut(.*); - - /** - * Walk the page table stored in dtim according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - function logic [`XLEN-1:0] adrTranslator( - input logic [`XLEN-1:0] adrIn); - begin - logic SvMode, PTE_R, PTE_X; - logic [`XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [0:2]; - logic [11:0] Offset; - - int i; - - // Grab the SATP register from privileged unit - SATP = dut.hart.priv.csr.SATP_REGW; - - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - - // We do not support sv48; only sv39 - SvMode = SATP[63]; - - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - - // dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.dtim.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R || PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction - - // initialize test - initial - begin - reset <= 1; # 22; reset <= 0; - end - - // read pc trace file - integer data_file_PC, scan_file_PC; - initial begin - data_file_PC = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); - if (data_file_PC == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - integer data_file_PCW, scan_file_PCW; - initial begin - data_file_PCW = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r"); - if (data_file_PCW == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read register trace file - integer data_file_rf, scan_file_rf; - initial begin - data_file_rf = $fopen({`LINUX_TEST_VECTORS,"parsedRegs.txt"}, "r"); - if (data_file_rf == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read CSR trace file - integer data_file_csr, scan_file_csr; - initial begin - data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r"); - if (data_file_csr == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read memreads trace file - integer data_file_memR, scan_file_memR; - initial begin - data_file_memR = $fopen({`LINUX_TEST_VECTORS,"parsedMemRead.txt"}, "r"); - if (data_file_memR == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // read memwrite trace file - integer data_file_memW, scan_file_memW; - initial begin - data_file_memW = $fopen({`LINUX_TEST_VECTORS,"parsedMemWrite.txt"}, "r"); - if (data_file_memW == 0) begin - $display("file couldn't be opened"); - $stop; - end - end - - // initial loading of memories - initial begin - $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); // load at address 0x1000, start of boot TIM - $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); - $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); - end - - integer warningCount = 0; - integer instrs; - - //logic[63:0] adrTranslation[4:0]; - //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"}; - //initial begin - // for(int i=0; i<5; i++) begin - // adrTranslation[i] = 64'b0; - // end - //end - - //function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); - // if (adr[11:0] !== adrExpected[11:0]) begin - // equal = 1'b0; - // end else begin - // equal = 1'b1; - // if ((adr+adrTranslation[func]) !== adrExpected) begin - // adrTranslation[func] = adrExpected - adr; - // $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs); - // warningCount += 1; - // end - // end - //endfunction - - // pretty sure this isn't necessary anymore, but keeping this for now since its easier - function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); - equal = adr === adrExpected; - endfunction - - - `define ERROR \ - #10; \ - $display("processed %0d instructions with %0d warnings", instrs, warningCount); \ - $stop; - - logic [63:0] pcExpected; - logic [63:0] regExpected; - integer regNumExpected; - logic [`XLEN-1:0] PCW; - - flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); - - genvar i; - generate - for(i=1; i<32; i++) begin - always @(dut.hart.ieu.dp.regf.rf[i]) begin - if ($time == 0) begin - scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); - if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin - $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); - `ERROR - end - end else begin - scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); - scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); - if (i != regNumExpected) begin - $display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]); - `ERROR - end - if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin - $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); - `ERROR - end - //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin - // force dut.hart.ieu.dp.regf.rf[i] = regExpected; - // release dut.hart.ieu.dp.regf.rf[i]; - //end - end - end - end - endgenerate - - // RAM and bootram are addressed in 64-bit blocks - this logic handles R/W - // including subwords. Brief explanation on signals: - // - // readMask: bitmask of bits to read / write, left-shifted to align with - // nearest 64-bit boundary - examples - // HSIZE = 0 -> readMask = 11111111 - // HSIZE = 1 -> readMask = 1111111111111111 - // - // In the linux boot, the processor spends the first ~5 instructions in - // bootram, before jr jumps to main RAM - - logic [63:0] readMask; - assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; - - logic [`XLEN-1:0] readAdrExpected, readAdrTranslated; - - always @(dut.HRDATA) begin - #2; - if (dut.hart.MemRWM[1] - && (dut.hart.ebu.CaptureDataM) - && dut.HRDATA !== {64{1'bx}}) begin - //$display("%0t", $time); - if($feof(data_file_memR)) begin - $display("no more memR data to read"); - `ERROR - end - scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); - scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); - assign readAdrTranslated = adrTranslator(readAdrExpected); - if (~equal(HADDR,readAdrTranslated,4)) begin - $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrTranslated); - `ERROR - end - if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin - if (HADDR inside `LINUX_FIX_READ) begin - //$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA); - force dut.uncore.HRDATA = HRDATA; - #9; - release dut.uncore.HRDATA; - warningCount += 1; - end else begin - $display("%0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); - `ERROR - end - end - //end else if(dut.hart.MemRWM[1]) begin - // $display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time); - - end - - end - - logic [`XLEN-1:0] writeDataExpected, writeAdrExpected, writeAdrTranslated; - - // this might need to change - //always @(HWDATA or HADDR or HSIZE or HWRITE) begin - always @(negedge HWRITE) begin - //#1; - if ($time != 0) begin - if($feof(data_file_memW)) begin - $display("no more memW data to read"); - `ERROR - end - scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); - scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); - assign writeAdrTranslated = adrTranslator(writeAdrExpected); - - if (writeDataExpected != HWDATA && ~dut.uncore.HSELPLICD) begin - $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); - `ERROR - end - if (~equal(writeAdrTranslated,HADDR,1) && ~dut.uncore.HSELPLICD) begin - $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrTranslated); - `ERROR - end - end - end - - integer totalCSR = 0; - logic [99:0] StartCSRexpected[63:0]; - string StartCSRname[99:0]; - initial begin - while(1) begin - scan_file_csr = $fscanf(data_file_csr, "%s\n", StartCSRname[totalCSR]); - if(StartCSRname[totalCSR] == "---") begin - break; - end - scan_file_csr = $fscanf(data_file_csr, "%x\n", StartCSRexpected[totalCSR]); - totalCSR = totalCSR + 1; - end - end - - always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin - if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin - $display("!!!!!! illegal instruction !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR); - `ERROR - end - if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin - $display("!!!!!! illegal (physical) memory access !!!!!!!!!!"); - $display("(as a reminder, MCAUSE and MEPC are set by this)"); - $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR); - `ERROR - end - end - - `define CHECK_CSR2(CSR, PATH) \ - string CSR; \ - logic [63:0] expected``CSR``; \ - //CSR checking \ - always @(``PATH``.``CSR``_REGW) begin \ - if ($time > 1) begin \ - if ("SEPC" == `"CSR`") begin #1; end \ - if ("SCAUSE" == `"CSR`") begin #2; end \ - if ("SSTATUS" == `"CSR`") begin #3; end \ - scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \ - scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ - if(CSR.icompare(`"CSR`")) begin \ - $display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \ - end \ - if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \ - $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ - `ERROR \ - end \ - end else begin \ - if (!(`BUILDROOT == 1 && "MSTATUS" == `"CSR`")) begin \ - for(integer j=0; j Date: Fri, 18 Jun 2021 09:11:31 -0400 Subject: [PATCH 21/30] Changed physical addresses to PA_BITS in size in MMU and TLB --- wally-pipelined/src/dmem/dmem.sv | 16 ++++++++++++---- wally-pipelined/src/ifu/ifu.sv | 11 ++++++++++- wally-pipelined/src/mmu/mmu.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 8 +++----- 4 files changed, 26 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index d05d592cb..657913009 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -87,6 +87,8 @@ module dmem ( logic [1:0] CurrState, NextState; logic preCommittedM; + logic [`PA_BITS-1:0] MemPAdrMmmu; + localparam STATE_READY = 0; localparam STATE_FETCH = 1; localparam STATE_FETCH_AMO = 2; @@ -95,10 +97,16 @@ module dmem ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + generate + if (`XLEN==32) + assign MemPAdrM = MemPAdrMmmu[31:0]; + else + assign MemPAdrM = {8'b0, MemPAdrMmmu}; + endgenerate mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), + .PhysicalAddress(MemPAdrMmmu), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), @@ -142,20 +150,20 @@ module dmem ( // Handle atomic load reserved / store conditional generate if (`A_SUPPORTED) begin // atomic instructions supported - logic [`XLEN-1:2] ReservationPAdrW; + logic [`PA_BITS-1:2] ReservationPAdrW; logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; assign lrM = MemReadM && AtomicM[0]; assign scM = MemRWM[0] && AtomicM[0]; - assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW; + assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else ReservationValidM = ReservationValidW; // otherwise don't change valid end - flopenrc #(`XLEN-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`XLEN-1:2], ReservationPAdrW); // could drop clear on this one but not valid + flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW); end else begin // Atomic operations not supported diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 29d77f091..ca0071b11 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -105,10 +105,19 @@ module ifu ( logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + logic [`PA_BITS-1:0] PCPFmmu; + + generate + if (`XLEN==32) + assign PCPF = PCPFmmu[31:0]; + else + assign PCPF = {8'b0, PCPFmmu}; + endgenerate + mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), - .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), + .PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else? diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 3efc4cef6..04deb694c 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -57,7 +57,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 86fe6f869..127dc5a53 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -78,7 +78,7 @@ module tlb #(parameter ENTRY_BITS = 3, input logic TLBFlush, // Physical address outputs - output logic [`XLEN-1:0] PhysicalAddress, + output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, @@ -202,11 +202,9 @@ module tlb #(parameter ENTRY_BITS = 3, // Output the hit physical address if translation is currently on. generate if (`XLEN == 32) begin - // *** If we want rv32 to use the full 34 bit physical address space, this - // must be changed - mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress); end else begin - mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, Translate, PhysicalAddress); + mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); end endgenerate From 21a55458ca7bd6d0607a39ff4508c2efda02289c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 09:36:22 -0400 Subject: [PATCH 22/30] Made MemPAdrM and related signals PA_BITS wide --- wally-pipelined/src/dmem/dcache.sv | 12 ++++++------ wally-pipelined/src/dmem/dmem.sv | 12 ++---------- wally-pipelined/src/ebu/ahblite.sv | 2 +- wally-pipelined/src/wally/wallypipelinedhart.sv | 3 ++- 4 files changed, 11 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/dmem/dcache.sv b/wally-pipelined/src/dmem/dcache.sv index 243c69759..fec70ef4b 100644 --- a/wally-pipelined/src/dmem/dcache.sv +++ b/wally-pipelined/src/dmem/dcache.sv @@ -31,7 +31,7 @@ module dcache( input logic StallW, input logic FlushW, // Upper bits of physical address - input logic [`XLEN-1:12] UpperPAdrM, + input logic [`PA_BITS-1:12] UpperPAdrM, // Lower 12 bits of virtual address, since it's faster this way input logic [11:0] LowerVAdrM, // Write to the dcache @@ -41,7 +41,7 @@ module dcache( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // Access requested from the ebu unit - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, // High if the dcache is requesting a stall output logic DCacheStallW, @@ -56,7 +56,7 @@ module dcache( // Input signals to cache memory logic FlushMem; - logic [`XLEN-1:12] DCacheMemUpperPAdr; + logic [`PA_BITS-1:12] DCacheMemUpperPAdr; logic [11:0] DCacheMemLowerAdr; logic DCacheMemWriteEnable; logic [DCACHELINESIZE-1:0] DCacheMemWriteData; @@ -98,7 +98,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:12] DCacheMemUpperPAdr, + input logic [`PA_BITS-1:12] DCacheMemUpperPAdr, // The lower bits of the virtual pc input logic [11:0] DCacheMemLowerAdr, @@ -122,7 +122,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( input logic [`XLEN-1:0] ReadDataW, input logic MemAckW, // The read we request from main memory - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM ); @@ -144,7 +144,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( logic FetchState, BeginFetchState; logic [LOGWPL:0] FetchWordNum, NextFetchWordNum; - logic [`XLEN-1:0] LineAlignedPCPF; + logic [`PA_BITS-1:0] LineAlignedPCPF; flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState); flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum); diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 657913009..ba3617d05 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -40,7 +40,7 @@ module dmem ( input logic [`XLEN-1:0] WriteDataM, input logic [1:0] AtomicM, input logic CommitM, - output logic [`XLEN-1:0] MemPAdrM, + output logic [`PA_BITS-1:0] MemPAdrM, output logic MemReadM, MemWriteM, output logic [1:0] AtomicMaskedM, output logic DataMisalignedM, @@ -87,8 +87,6 @@ module dmem ( logic [1:0] CurrState, NextState; logic preCommittedM; - logic [`PA_BITS-1:0] MemPAdrMmmu; - localparam STATE_READY = 0; localparam STATE_FETCH = 1; localparam STATE_FETCH_AMO = 2; @@ -97,16 +95,10 @@ module dmem ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. - generate - if (`XLEN==32) - assign MemPAdrM = MemPAdrMmmu[31:0]; - else - assign MemPAdrM = {8'b0, MemPAdrMmmu}; - endgenerate mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), - .PhysicalAddress(MemPAdrMmmu), .TLBMiss(DTLBMissM), + .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ea76556cb..88e8f27ab 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -47,7 +47,7 @@ module ahblite ( output logic [`XLEN-1:0] InstrRData, output logic InstrAckF, // Signals from Data Cache - input logic [`XLEN-1:0] MemPAdrM, + input logic [`PA_BITS-1:0] MemPAdrM, input logic MemReadM, MemWriteM, input logic [`XLEN-1:0] WriteDataM, input logic [1:0] MemSizeM, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 2535eef3d..c2dfd4371 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -135,7 +135,8 @@ module wallypipelinedhart ( logic MemReadM, MemWriteM; logic [1:0] AtomicMaskedM; logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; + logic [`XLEN-1:0] MemAdrM, WriteDataM; + logic [`PA_BITS-1:0] MemPAdrM; logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData; From 72f1e3eab61e93c61f77e5f9fab658e076194ed0 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 09:49:30 -0400 Subject: [PATCH 23/30] buildroot added to regression because it passes regression --- wally-pipelined/regression/regression-wally.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 5b45f9a59..d3afe6edc 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -28,11 +28,11 @@ configs = [ cmd="vsim -do wally-busybear-batch.do -c > {}", grepstr="# loaded 100000 instructions" ), -# TestCase( -# name="buildroot", -# cmd="vsim -do wally-buildroot-batch.do -c > {}", -# grepstr="# loaded 100000 instructions" -# ), + TestCase( + name="buildroot", + cmd="vsim -do wally-buildroot-batch.do -c > {}", + grepstr="# loaded 600000 instructions" + ), TestCase( name="rv32ic", cmd="vsim > {} -c < Date: Fri, 18 Jun 2021 11:46:25 -0400 Subject: [PATCH 24/30] Updated directory coremark_bare's wally-config file to define PMP_ENTRIES --- wally-pipelined/config/coremark_bare/wally-config.vh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 5b62a23e0..828dd084a 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -52,6 +52,9 @@ `define ITLB_ENTRY_BITS 5 `define DTLB_ENTRY_BITS 5 +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 16 + // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -101,7 +104,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 -/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" +`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE"//comments From 958f60c7049a67b51650ca058f4e63b979326fb1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 11:58:16 -0400 Subject: [PATCH 25/30] restore graphical buildroot sim --- wally-pipelined/testbench/testbench-linux.sv | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 9f80a33d4..f9d2415e1 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -474,18 +474,18 @@ module testbench(); end string PCtextD,PCtextE,PCtextM,PCtext2; - always_ff @(posedge clk, posedge reset) - if (reset) begin - PCtextE <= #1 "(reset)"; - PCtextM <= #1 "(reset)"; - end else begin - if (~dut.hart.StallE) - if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; - else PCtextE <= #1 PCtextD; - if (~dut.hart.StallM) - if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; - else PCtextM <= #1 PCtextE; - end + //always_ff @(posedge clk, posedge reset) + // if (reset) begin + // PCtextE <= #1 "(reset)"; + // PCtextM <= #1 "(reset)"; + // end else begin + // if (~dut.hart.StallE) + // if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; + // else PCtextE <= #1 PCtextD; + // if (~dut.hart.StallM) + // if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; + // else PCtextM <= #1 PCtextE; + // end initial begin From 43bc17350be57d64e41cf6bb2397227b58f55be8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 18 Jun 2021 12:36:25 -0400 Subject: [PATCH 26/30] Restored wally-busybear testbench now that graphical sim is working --- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-linux.sv | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 0be7fcdd9..11876dded 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt vsim workopt -suppress 8852,12070 -#do ./wave-dos/linux-waves.do +do ./wave-dos/linux-waves.do #-- Run the Simulation diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index f9d2415e1..b3552cb1a 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -498,10 +498,8 @@ module testbench(); always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin if(~HWRITE) begin #2; - $display("test point"); if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin if (dut.hart.ifu.PCD !== lastPCD) begin - $display("tp2"); lastCheckInstrD = CheckInstrD; lastPC <= dut.hart.ifu.PCD; lastPC2 <= lastPC; @@ -528,22 +526,16 @@ module testbench(); end end else begin - $display("tp4"); if($feof(data_file_PC)) begin $display("no more PC data to read"); `ERROR end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; - $display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); while (PCtext2 != "***") begin - $display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); PCtextD = {PCtextD, " ", PCtext2}; - $display("tp8"); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); - $display("tp9"); end - $display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); if(dut.hart.ifu.PCD === pcExpected) begin if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs From d4de8a54a28e25304c1d7575a0620f23c92b35dd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Jun 2021 12:02:59 -0500 Subject: [PATCH 27/30] Icache now uses physical lenght bits rather than XLEN. --- wally-pipelined/src/cache/ICacheCntrl.sv | 14 +++++++------- wally-pipelined/src/cache/ICacheMem.sv | 10 +++++----- wally-pipelined/src/cache/icache.sv | 6 +++--- wally-pipelined/src/ifu/ifu.sv | 4 +++- 4 files changed, 18 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index d8383965a..9037748c5 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // Input the address to read // The upper bits of the physical pc - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Signals to/from cache memory // The read coming out of it input logic [31:0] ICacheMemReadData, input logic ICacheMemReadValid, // The address at which we want to search the cache memory - output logic [`XLEN-1:0] PCTagF, - output logic [`XLEN-1:0] PCNextIndexF, + output logic [`PA_BITS-1:0] PCTagF, + output logic [`PA_BITS-1:0] PCNextIndexF, output logic ICacheReadEn, // Load data into the cache output logic ICacheMemWriteEnable, @@ -133,8 +133,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF; - logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPFinalF, PCSpillF; + logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; logic [31:0] FinalInstrRawF; @@ -174,7 +174,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( assign PCNextIndexF = PCPFinalF; // truncate the offset from PCPF for memory address generation - assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH]; + assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; // Detect if the instruction is compressed assign CompressedF = FinalInstrRawF[1:0] != 2'b11; diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index 4ea3d22a6..9a5fdbe2f 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) // If flush is high, invalidate the entire cache input logic flush, - input logic [`XLEN-1:0] PCTagF, // physical address - input logic [`XLEN-1:0] PCNextIndexF, // virtual address + input logic [`PA_BITS-1:0] PCTagF, // physical address + input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address input logic WriteEnable, input logic [BLOCKLEN-1:0] WriteLine, output logic [BLOCKLEN-1:0] ReadLineF, @@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) localparam OFFSETLEN = $clog2(BLOCKBYTELEN); localparam INDEXLEN = $clog2(NUMLINES); // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48 - localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; + localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; logic [TAGLEN-1:0] LookupTag; logic [NUMLINES-1:0] ValidOut; @@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) cachetags (.*, .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .ReadData(LookupTag), - .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) + .WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]) ); // Correctly handle the valid bits @@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) end DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; end - assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); + assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]); endmodule diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index e3a0829be..907d30fa0 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -31,8 +31,8 @@ module icache input logic clk, reset, input logic StallF, StallD, input logic FlushD, - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, // Data read in from the ebu unit input logic [`XLEN-1:0] InstrInF, input logic InstrAckF, @@ -58,7 +58,7 @@ module icache logic ICacheMemWriteEnable; logic [BLOCKLEN-1:0] ICacheMemWriteData; logic EndFetchState; - logic [`XLEN-1:0] PCTagF, PCNextIndexF; + logic [`PA_BITS-1:0] PCTagF, PCNextIndexF; // Output signals from cache memory logic [31:0] ICacheMemReadData; logic ICacheMemReadValid; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ca0071b11..275cee767 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -138,7 +138,9 @@ module ifu ( // jarred 2021-03-14 Add instrution cache block to remove rd2 assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live - icache icache(.*); + icache icache(.*, + .PCNextF(PCNextF[`PA_BITS-1:0]), + .PCPF(PCPFmmu)); From 22ea801edb2268e5b1ad4ccf2535de6f19ad01d4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 18 Jun 2021 12:05:02 -0500 Subject: [PATCH 28/30] Improved some names in icache. --- wally-pipelined/src/cache/ICacheCntrl.sv | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 9037748c5..d73a85bc1 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -133,7 +133,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`PA_BITS-1:0] PCPreFinalF, PCPFinalF, PCSpillF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; @@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. - assign PCSpillF = PCPF + `XLEN'b10; + assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width. // now we have to select between these three PCs assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary - assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; + assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF; // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // *** read enable may not be necessary. @@ -170,8 +170,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( .d(PCMux), .q(PCMux_q)); - assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF; - assign PCNextIndexF = PCPFinalF; + assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF; // truncate the offset from PCPF for memory address generation assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; @@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // more zeros after the addition. This will be the number of offset bits less the AHBByteLength. - logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; + logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}}; // verilator lint_off WIDTH From f84a689c19a8939f1a958795e83b22e737f9ad7d Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 18 Jun 2021 17:37:40 -0400 Subject: [PATCH 29/30] fixed PCtext error by using blocking assignments --- wally-pipelined/testbench/testbench-linux.sv | 32 ++++++++------------ 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index f9d2415e1..10a1795dc 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -474,18 +474,18 @@ module testbench(); end string PCtextD,PCtextE,PCtextM,PCtext2; - //always_ff @(posedge clk, posedge reset) - // if (reset) begin - // PCtextE <= #1 "(reset)"; - // PCtextM <= #1 "(reset)"; - // end else begin - // if (~dut.hart.StallE) - // if (dut.hart.FlushE) PCtextE <= #1 "(flushed)"; - // else PCtextE <= #1 PCtextD; - // if (~dut.hart.StallM) - // if (dut.hart.FlushM) PCtextM <= #1 "(flushed)"; - // else PCtextM <= #1 PCtextE; - // end + always_ff @(posedge clk, posedge reset) + if (reset) begin + PCtextE = "(reset)"; + PCtextM = "(reset)"; + end else begin + if (~dut.hart.StallM) + if (dut.hart.FlushM) PCtextM = "(flushed)"; + else PCtextM = PCtextE; + if (~dut.hart.StallE) + if (dut.hart.FlushE) PCtextE = "(flushed)"; + else PCtextE = PCtextD; + end initial begin @@ -498,10 +498,8 @@ module testbench(); always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin if(~HWRITE) begin #2; - $display("test point"); if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin if (dut.hart.ifu.PCD !== lastPCD) begin - $display("tp2"); lastCheckInstrD = CheckInstrD; lastPC <= dut.hart.ifu.PCD; lastPC2 <= lastPC; @@ -528,22 +526,16 @@ module testbench(); end end else begin - $display("tp4"); if($feof(data_file_PC)) begin $display("no more PC data to read"); `ERROR end scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD); PCtext2 = ""; - $display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); while (PCtext2 != "***") begin - $display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); PCtextD = {PCtextD, " ", PCtext2}; - $display("tp8"); scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); - $display("tp9"); end - $display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD); if(dut.hart.ifu.PCD === pcExpected) begin if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs