From a99fc74976ad605ee57875645debfbe2c8cc55f7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 14:40:06 -0800 Subject: [PATCH] Removed integer from localparams --- pipelined/src/cache/cacheLRU.sv | 6 ++--- pipelined/src/cache/cacheway.sv | 16 ++++++------- pipelined/src/ebu/ahbcacheinterface.sv | 12 +++++----- pipelined/src/ifu/bpred/foldedgshare.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 8 +++---- pipelined/src/ifu/spill.sv | 8 +++---- pipelined/src/lsu/lsu.sv | 16 ++++++------- pipelined/testbench/sdc/sd_top_tb.sv | 2 +- pipelined/testbench/testbench.sv | 30 ++++++++++++------------- 9 files changed, 49 insertions(+), 53 deletions(-) diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index be42036e0..2e3057f0c 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -81,8 +81,8 @@ module cacheLRU // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ... for(row = 0; row < LOGNUMWAYS; row++) begin localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1); - localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1; - localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2; + localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1; + localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2; assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}}; end @@ -109,8 +109,6 @@ module cacheLRU for(s = NUMWAYS/2-1; s >= 0; s--) begin localparam int0 = (NUMWAYS/2-1-s)*2; localparam int1 = int0 + 1; - //localparam int0 = s*2; - //localparam int1 = int0 + 1; assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d3e996729..671bbcaff 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -55,11 +55,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, output logic DirtyWay, // This way is dirty output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid - localparam integer WORDSPERLINE = LINELEN/`XLEN; - localparam integer BYTESPERLINE = LINELEN/8; + localparam WORDSPERLINE = LINELEN/`XLEN; + localparam BYTESPERLINE = LINELEN/8; localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer BYTESPERWORD = `XLEN/8; + localparam BYTESPERWORD = `XLEN/8; logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; @@ -128,12 +128,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, // Data Array ///////////////////////////////////////////////////////////////////////////////////////////// - genvar words; + genvar words; - localparam integer SRAMLEN = 128; - localparam integer NUMSRAM = LINELEN/SRAMLEN; - localparam integer SRAMLENINBYTES = SRAMLEN/8; - localparam integer LOGNUMSRAM = $clog2(NUMSRAM); + localparam SRAMLEN = 128; + localparam NUMSRAM = LINELEN/SRAMLEN; + localparam SRAMLENINBYTES = SRAMLEN/8; + localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 8bd1bc083..7278f4f93 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -72,12 +72,12 @@ module ahbcacheinterface #( output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt - localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation - logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage - logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data + localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index + logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage + logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv index 9de5d5c95..85b7db383 100644 --- a/pipelined/src/ifu/bpred/foldedgshare.sv +++ b/pipelined/src/ifu/bpred/foldedgshare.sv @@ -54,13 +54,13 @@ module foldedgshare #(parameter k = 16, depth = 10) ( logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE, IndexM, IndexW; - logic [depth-1:0] FinalIndexNextF, FinalIndexW; + logic [depth-1:0] FinalIndexNextF, FinalIndexW; logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - localparam int delta = 2 * depth - k; + localparam delta = 2 * depth - k; assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 476f666ff..0ff6dc3f9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -210,11 +210,11 @@ module ifu ( end if (`BUS) begin : bus // **** must fix words per line vs beats per line as in lsu. - localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; - localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; + localparam WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; + localparam LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache - localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + localparam LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; + localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv index 9df9fca18..aa93c4397 100644 --- a/pipelined/src/ifu/spill.sv +++ b/pipelined/src/ifu/spill.sv @@ -50,15 +50,15 @@ module spill #( output logic CompressedF); // The fetched instruction is compressed // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1] - localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; + typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; + statetype CurrState, NextState; + localparam SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; logic [`XLEN-1:0] PCPlus2F; logic TakeSpillF; logic SpillF; logic SelSpillF; - logic SpillSaveF; + logic SpillSaveF; logic [15:0] InstrFirstHalf; - typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; - statetype CurrState, NextState; //////////////////////////////////////////////////////////////////////////////////////////////////// // PC logic diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f89fe0da4..19f5ba960 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -238,12 +238,12 @@ module lsu ( end if (`BUS) begin : bus if(`DCACHE) begin : dcache - localparam integer LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline - localparam integer LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ - localparam integer BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline - localparam integer AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^ - localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline + localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^ + localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline + localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^ + localparam LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline + localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline logic [`PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback. @@ -251,10 +251,10 @@ module lsu ( logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface - logic [1:0] BusRW; // Uncached bus memory access + logic [1:0] BusRW; // Uncached bus memory access logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) - logic [1:0] CacheAtomicM; // Cache AMO + logic [1:0] CacheAtomicM; // Cache AMO assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/pipelined/testbench/sdc/sd_top_tb.sv index 3282c0e2a..65d9ed454 100644 --- a/pipelined/testbench/sdc/sd_top_tb.sv +++ b/pipelined/testbench/sdc/sd_top_tb.sv @@ -32,7 +32,7 @@ module sd_top_tb(); - localparam integer g_COUNT_WIDTH = 8; + localparam g_COUNT_WIDTH = 8; logic a_RST; logic i_SD_CMD; diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5456ce8b9..fbd720109 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -205,8 +205,8 @@ logic [3:0] dummy; InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests - localparam integer MemStartAddr = 0; - localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); + localparam MemStartAddr = 0; + localparam MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); initial begin @@ -570,25 +570,23 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; if(`DCACHE) begin - localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; - -//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM; - localparam integer numwords = sramlen/`XLEN; - localparam integer lognumlines = $clog2(numlines); - localparam integer loglinebytelen = $clog2(linebytelen); - localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + loglinebytelen; + localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; + localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; + localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; + localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam numwords = sramlen/`XLEN; + localparam lognumlines = $clog2(numlines); + localparam loglinebytelen = $clog2(linebytelen); + localparam lognumways = $clog2(numways); + localparam tagstart = lognumlines + loglinebytelen; genvar index, way, cacheWord; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic [sramlen-1:0] cacheline; + logic [sramlen-1:0] cacheline; logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];