From a91dcd83721ef9ea1f6a370c2543412bab2d352c Mon Sep 17 00:00:00 2001
From: Matthew <106996253+Matthew-Otto@users.noreply.github.com>
Date: Tue, 25 Jun 2024 15:31:20 -0500
Subject: [PATCH] Fix progbufaddr size

---
 src/debug/dm.sv                 | 7 +++++--
 src/ifu/ifu.sv                  | 4 +---
 src/ifu/progbuf.sv              | 2 +-
 src/wally/wallypipelinedcore.sv | 4 +---
 src/wally/wallypipelinedsoc.sv  | 4 +---
 5 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/debug/dm.sv b/src/debug/dm.sv
index 3e8f25a9b..410a47c4c 100644
--- a/src/debug/dm.sv
+++ b/src/debug/dm.sv
@@ -68,7 +68,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
   output logic            DebugRegUpdate, // writes values from scan register after scanning in			
   
   // Program Buffer
-  output logic [$clog2(PROGBUF_SIZE)-1:0]      ProgBufAddr,
+  output logic [P.XLEN-1:0] ProgBufAddr,
   output logic            ProgBuffScanEn,
   output logic            ExecProgBuf
 );
@@ -88,6 +88,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic                       RspValid;
   logic [31:0]                RspData;
   logic [1:0]                 RspOP;
+  logic [P.XLEN-`DMI_ADDR_WIDTH-1:0] UpperReqAddr;
 
   // JTAG ID for Wally:  
   // Version [31:28] = 0x1 : 0001
@@ -174,6 +175,8 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic [2:0]        CmdErr;
   const logic [3:0]  DataCount = DATA_COUNT[3:0];
 
+  assign UpperReqAddr = '0;
+
   // Core control signals
   assign AllHaveReset = HaveReset;
   assign AnyHaveReset = HaveReset;
@@ -373,7 +376,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
             CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
           else begin
             NewAcState <= PROGBUFF_WRITE;
-            ProgBufAddr <= ReqAddress[$clog2(PROGBUF_SIZE)-1:0];
+            ProgBufAddr <= {UpperReqAddr, ReqAddress};
           end
           RspOP <= `OP_SUCCESS;
           State <= ACK;
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 38b109103..e5d64716c 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -100,15 +100,13 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   input  logic                 DRet,
   input  logic                 ProgBuffScanEn,
   // Debug scan chain
-  input  logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr,
+  input  logic [P.XLEN-1:0]    ProgBufAddr,
   input  logic                 ProgBufScanIn,
   input  logic                 DebugScanEn,
   input  logic                 DebugScanIn,
   output logic                 DebugScanOut
 );
 
-  localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
-
   localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
   localparam            LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
 
diff --git a/src/ifu/progbuf.sv b/src/ifu/progbuf.sv
index a1d6ed0fa..9b8afe38c 100644
--- a/src/ifu/progbuf.sv
+++ b/src/ifu/progbuf.sv
@@ -31,7 +31,7 @@ module progbuf import cvw::*;  #(parameter cvw_t P) (
     input  logic [5:0]  Addr,
     output logic [31:0] ProgBufInstrF,
 
-    input  logic [$clog2(PROGBUF_SIZE)-1:0] ScanAddr,
+    input  logic [P.XLEN-1:0] ScanAddr,
     input  logic        Scan,
     input  logic        ScanIn
 );
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 8a01dcf8b..8b47378af 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -68,12 +68,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    input  logic [11:0]           DebugRegAddr,   // address for scanable regfiles (GPR, FPR, CSR)
    input  logic                  DebugCapture,   // latches values into scan register before scanning out
    input  logic                  DebugRegUpdate,  // writes values from scan register after scanning in	
-   input  logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr,
+   input  logic [P.XLEN-1:0]     ProgBufAddr,
    input  logic                  ProgBuffScanEn
 );
 
-  localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
-
   logic                          StallF, StallD, StallE, StallM, StallW;
   logic                          FlushD, FlushE, FlushM, FlushW;
   logic                          TrapM, RetM;
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index e7c73e7a5..20a570f04 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -98,11 +98,9 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   logic [11:0]                 DebugRegAddr;
   logic                        DebugCapture;
   logic                        DebugRegUpdate;
-  logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr;
+  logic [P.XLEN-1:0]           ProgBufAddr;
   logic                        ProgBuffScanEn;
 
-  localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
-
   // synchronize reset to SOC clock domain
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset));