From a8faddf81f0404680ff5350411e0fbb43eb04a1d Mon Sep 17 00:00:00 2001 From: Daniel Torres Date: Thu, 21 Jul 2022 12:47:51 -0700 Subject: [PATCH] removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes --- pipelined/testbench/testbench.sv | 29 +- pipelined/testbench/tests.vh | 1152 ++++++++++---------- tests/riscof/Makefile | 8 +- tests/riscof/sail_cSim/riscof_sail_cSim.py | 4 +- 4 files changed, 607 insertions(+), 586 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0fb5f5e60..30c62865e 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -195,13 +195,19 @@ logic [3:0] dummy; /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ - memfilename = {pathname, tests[test], ".elf.memfile"}; + if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else memfilename = {pathname, tests[test], ".elf.memfile"}; if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); - ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; - ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + if (riscofTest) begin + ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else begin + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + end // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); @@ -241,7 +247,8 @@ logic [3:0] dummy; // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking $display("Embench Benchmark: %s is done.", tests[test]); - outputfile = {pathname, tests[test], ".sim.output"}; + if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; + else outputfile = {pathname, tests[test], ".sim.output"}; outputFilePointer = $fopen(outputfile); i = 0; while ($unsigned(i) < $unsigned(5'd5)) begin @@ -256,7 +263,7 @@ logic [3:0] dummy; for(i=0; i config$(XLEN).ini -build_arch: +fsd_fld_tempfix: + # this is a temporary fix, there's a typo on the rv64i_m/D/src/d_fsd-align-01.S and rv64i_m/D/src/d_fld-align-01.S tests + # https://github.com/riscv-non-isa/riscv-arch-test/issues/266 + find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*fld*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {} + find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*fsd*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {} + +build_arch: fsd_fld_tempfix riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser rm -rf $(arch_workdir)/rv$(XLEN)i_m mv -f $(work_dir)/rv$(XLEN)i_m $(arch_workdir)/ diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index b86f62b55..dc3033ab3 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -90,7 +90,7 @@ class sail_cSim(pluginTemplate): test_dir = testentry['work_dir'] test_name = test.rsplit('/',1)[1][:-2] - elf = 'Ref.elf' + elf = 'ref.elf' execute = "@cd "+testentry['work_dir']+";" @@ -98,7 +98,7 @@ class sail_cSim(pluginTemplate): compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) execute+=compile_cmd+";" - execute += self.objdump_cmd.format(elf, self.xlen, 'Ref.elf.objdump') + execute += self.objdump_cmd.format(elf, self.xlen, 'ref.elf.objdump') sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") execute += self.sail_exe[self.xlen] + ' -z268435455 --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)