Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed output delay in synthesis

Browse Source
This commit is contained in:
David Harris 2023-01-31 04:37:23 -08:00
parent 6777fd9b55
commit a8f268e2a4
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
synthDC/scripts/synth.tcl
View File

@ -134,8 +134,8 @@ if {$tech == "sky130"} {
# Set input/output delay # Set input/output delay
if {$drive == "FLOP"} { if {$drive == "FLOP"} {
set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
set_output_delay 0.1 -max -clock $my_clk [all_outputs] set_output_delay 0.0 -max -clock $my_clk [all_outputs]
} else { } else {
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
set_output_delay 0.0 -max -clock $my_clk [all_outputs] set_output_delay 0.0 -max -clock $my_clk [all_outputs]