From a8f11dcad02d3c6f125020bdbcf6d3efb816fee5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Jun 2023 11:11:34 -0500 Subject: [PATCH] FPGA updates. --- fpga/constraints/debug2.xdc | 6 +++--- fpga/generator/wally.tcl | 2 +- fpga/src/wallypipelinedsocwrapper.sv | 2 +- testbench/testbench.sv | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 58e2fa643..f09acb6c1 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -1107,7 +1107,7 @@ connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 10 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][10]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe217] @@ -1132,12 +1132,12 @@ connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe221] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] +connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe222] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] +connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][2]} ]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe223] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 63dbc0b79..a28d42654 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -83,7 +83,7 @@ if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc } else { - source ../constraints/debug4.xdc + source ../constraints/vcu-small-debug.xdc } diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index 0ba69d167..bdde7f4fc 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -34,7 +34,7 @@ module wallypipelinedsocwrapper ( input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [P.AHBW-1:0] HRDATAEXT, + input logic [64-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4cab1a105..9ed35496d 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -35,7 +35,7 @@ module testbench; /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; parameter TEST="none"; - parameter PrintHPMCounters=0; + parameter PrintHPMCounters=1; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0;