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upgraded gpio bus interface

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bbracker 2021-03-25 00:15:02 -04:00
parent 77768cee5d
commit a8b7d7a248
1 changed files with 13 additions and 8 deletions
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21
wally-pipelined/src/uncore/gpio.sv
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@ -33,6 +33,8 @@ module gpio (
input logic [7:0] HADDR, input logic [7:0] HADDR,
input logic [`XLEN-1:0] HWDATA, input logic [`XLEN-1:0] HWDATA,
input logic HWRITE, input logic HWRITE,
input logic HREADY,
input logic [1:0] HTRANS,
output logic [`XLEN-1:0] HREADGPIO, output logic [`XLEN-1:0] HREADGPIO,
output logic HRESPGPIO, HREADYGPIO, output logic HRESPGPIO, HREADYGPIO,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
@ -40,15 +42,19 @@ module gpio (
logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL; logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
logic [7:0] entry; logic [7:0] entry, HADDRd;
logic memread, memwrite; logic initTrans, memread, memwrite;
assign memread = HSELGPIO & ~HWRITE; assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
assign memwrite = HSELGPIO & HWRITE;
// Control Signals
flopenr #(1) memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread);
flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite);
flopenr #(8) haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
// Response Signals
assign HRESPGPIO = 0; // OK assign HRESPGPIO = 0; // OK
always_ff @(posedge HCLK) // delay response to data cycle assign HREADYGPIO = 1; // never ask for wait states
HREADYGPIO <= memread | memwrite;
// assign HREADYGPIO = 1; // Respond immediately
// word aligned reads // word aligned reads
generate generate
@ -103,7 +109,6 @@ module gpio (
if (~HRESETn) begin if (~HRESETn) begin
INPUT_EN <= 0; INPUT_EN <= 0;
OUTPUT_EN <= 0; OUTPUT_EN <= 0;
//OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
end else if (memwrite) begin end else if (memwrite) begin
if (entry == 8'h04) INPUT_EN <= HWDATA; if (entry == 8'h04) INPUT_EN <= HWDATA;
if (entry == 8'h08) OUTPUT_EN <= HWDATA; if (entry == 8'h08) OUTPUT_EN <= HWDATA;