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temporary commit to help debug merging testbench.sv with testbench-imperas.sv

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This commit is contained in:
Rose Thompson 2024-05-17 12:36:00 -05:00
parent bd8450734b
commit a885240fbd
2 changed files with 2 additions and 2 deletions
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2
sim/questa/run-imperas-linux.sh
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@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
#export OTHERFLAGS=""
vsim -c -do "do wally.do buildroot buildroot testbench --lockstep"
vsim -do "do wally.do buildroot buildroot testbench --lockstep +acc -GDEBUG=1"

2
testbench/testbench-imperas.sv
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@ -97,7 +97,7 @@ module testbench;
initial
begin
ResetCount = 0;
ResetThreshold = 2;
ResetThreshold = 21;
InReset = 1;
testadr = 0;
testadrNoBase = 0;