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Merge pull request #679 from kevindkim723/extract_arch_test_fix
fixed bug in intdivrem test vector extraction
This commit is contained in:
Rose Thompson
GitHub
commit
a884c04b62
@ -1078,4 +1078,213 @@ IEEE754 1
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deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc
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IEEE754 1
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#### DIVIDER VARIANTS WITH IDIV ON FPU
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deriv f_ieee_div_2_1i_rv32gc f_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_2_2i_rv32gc f_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_2_4i_rv32gc f_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_4_1i_rv32gc f_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_4_2i_rv32gc f_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_2_1i_rv64gc f_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_2_2i_rv64gc f_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_2_4i_rv64gc f_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_4_1i_rv64gc f_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_4_2i_rv64gc f_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv f_ieee_div_4_4i_rv64gc f_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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#### FH_only, RK variable
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deriv fh_ieee_div_2_1i_rv32gc fh_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_2_2i_rv32gc fh_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_2_4i_rv32gc fh_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_4_1i_rv32gc fh_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_4_2i_rv32gc fh_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_2_1i_rv64gc fh_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_2_2i_rv64gc fh_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_2_4i_rv64gc fh_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_4_1i_rv64gc fh_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_4_2i_rv64gc fh_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv fh_ieee_div_4_4i_rv64gc fh_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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# FD only , rk variable
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deriv fd_ieee_div_2_1i_rv32gc fd_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_2_2i_rv32gc fd_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_2_4i_rv32gc fd_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_4_1i_rv32gc fd_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_4_2i_rv32gc fd_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_2_1i_rv64gc fd_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_2_2i_rv64gc fd_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_2_4i_rv64gc fd_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_4_1i_rv64gc fd_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_4_2i_rv64gc fd_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv fd_ieee_div_4_4i_rv64gc fd_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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# FDH only , rk variable
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deriv fdh_ieee_div_2_1i_rv32gc fdh_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_2_2i_rv32gc fdh_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_2_4i_rv32gc fdh_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_4_1i_rv32gc fdh_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_4_2i_rv32gc fdh_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_2_1i_rv64gc fdh_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_2_2i_rv64gc fdh_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_2_4i_rv64gc fdh_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_4_1i_rv64gc fdh_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_4_2i_rv64gc fdh_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdh_ieee_div_4_4i_rv64gc fdh_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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# FDQ only , rk variable
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deriv fdq_ieee_div_2_1i_rv32gc fdq_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_2_2i_rv32gc fdq_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_2_4i_rv32gc fdq_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_4_1i_rv32gc fdq_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_4_2i_rv32gc fdq_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_2_1i_rv64gc fdq_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_2_2i_rv64gc fdq_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_2_4i_rv64gc fdq_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_4_1i_rv64gc fdq_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_4_2i_rv64gc fdq_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdq_ieee_div_4_4i_rv64gc fdq_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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# FDQH only , rk variable
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deriv fdqh_ieee_div_2_1i_rv32gc fdqh_ieee_div_2_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_2_2i_rv32gc fdqh_ieee_div_2_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_2_4i_rv32gc fdqh_ieee_div_2_4_rv32gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_4_1i_rv32gc fdqh_ieee_div_4_1_rv32gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_4_2i_rv32gc fdqh_ieee_div_4_2_rv32gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_2_1i_rv64gc fdqh_ieee_div_2_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_2_2i_rv64gc fdqh_ieee_div_2_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_2_4i_rv64gc fdqh_ieee_div_2_4_rv64gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_4_1i_rv64gc fdqh_ieee_div_4_1_rv64gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_4_2i_rv64gc fdqh_ieee_div_4_2_rv64gc
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IDIV_ON_FPU 1
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deriv fdqh_ieee_div_4_4i_rv64gc fdqh_ieee_div_4_4_rv64gc
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IDIV_ON_FPU 1
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@ -116,6 +116,11 @@ def create_vectors(my_config):
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if "op1val" in line:
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# print("det2")
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# parse line
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# handle special case where destination register is hardwired to zero
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if "dest:x0" in line:
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answer = "x" * len(answer)
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals
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op2val = line.split("op2val")[1].split("x")[1].strip()
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@ -158,6 +163,9 @@ def create_vectors(my_config):
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if "op1val" in line:
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# print("det2")
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# parse line
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# handle special case where destination register is hardwired to zero
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if "dest:x0" in line:
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answer = "x" * len(answer)
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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@ -201,7 +209,12 @@ def create_vectors(my_config):
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if "op1val" in line:
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# print("det2")
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# parse line
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# handle special case where destination register is hardwired to zero
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if "dest:x0" in line:
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answer = "x" * len(answer)
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
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@ -243,6 +256,11 @@ def create_vectors(my_config):
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if "op1val" in line:
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# print("det2")
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# parse line
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# handle special case where destination register is hardwired to zero
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if "dest:x0" in line:
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answer = "x" * len(answer)
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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