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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Sold progress towards a decent q test.
This commit is contained in:
parent
1872966b0b
commit
a85ace87c7
@ -2,7 +2,35 @@
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00000000
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00000000
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00000000
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00000000
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3fff0000
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3fff0000
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00003f00 # fsh of 1
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dead4000 # fsh of 1
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deadbeef
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deadbeef
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deadbeef
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00000000 # fsq of 3
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00000000
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00000000
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00000000
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00000000
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40008000
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00000000 # fsq of -1
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00000000
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00000000
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00000000
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bfff0000
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00000000 # fsq of 6
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00000000
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00000000
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40018000
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00000000 # fsq of -4
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00000000
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00000000
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C0010000
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00000000 # fsq of -2
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00000000
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00000000
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C0000000
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00000000 # fsq of 4
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00000000
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00000000
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40010000
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00000000 # fsq of 2
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00000000
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00000000
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40000000
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@ -19,7 +19,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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#include "model_test.h"
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#include "model_test.h"
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#include "arch_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64IFDQ_Zicsr")
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RVTEST_ISA("RV64IFDQZfh_Zicsr")
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.section .text.init
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.section .text.init
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.globl rvtest_entry_point
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.globl rvtest_entry_point
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@ -47,7 +47,7 @@ li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000
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fcvt.q.w f2, x2
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fcvt.q.w f2, x2
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fcvt.q.w f4, x4
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fcvt.q.w f4, x4
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fcvt.h.w f5, x2
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fcvt.h.w f5, x2 # 4000
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# test quad load/store
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# test quad load/store
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fsq f4, 0(x3)
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fsq f4, 0(x3)
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@ -59,33 +59,33 @@ fsh f5, 16(x3)
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flh f6, 16(x3)
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flh f6, 16(x3)
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fsh f6, 16(x1)
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fsh f6, 16(x1)
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# 1 + 2 = 3 # 4000 1000 0000 0000 0000 0000 0000 0000
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# 1 + 2 = 3 # 4000 8000 0000 0000 0000 0000 0000 0000
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fadd.q f8, f2, f4
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fadd.q f8, f2, f4
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fsq f8, 32(x3)
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fsq f8, 32(x1)
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# 1 - 2 = -1
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# 1 - 2 = -1
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fsub.q f9, f2, f4 # bfff 0000000000000000000000000000
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fsub.q f9, f4, f2 # bfff 0000000000000000000000000000
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fsq f9, 48(x3)
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fsq f9, 48(x1)
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# 2 * 3 = 6
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# 2 * 3 = 6
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fsub.q f10, f4, f8 # 4001 1000000000000000000000000000
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fmul.q f10, f2, f8 # 4001 8000000000000000000000000000
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fsq f10, 64(x3)
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fsq f10, 64(x1)
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# 6 * (-1) + 2 = -4
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# 6 * (-1) + 2 = -4
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fmadd.q f11, f10, f9, f4 # C001 0000000000000000000000000000
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fmadd.q f11, f10, f9, f2 # C001 0000000000000000000000000000
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fsq f11, 80(x3)
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fsq f11, 80(x1)
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# -4 / 2 = -2
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# -4 / 2 = -2
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fdiv.q f12, f11, f4 # C000 0000000000000000000000000000
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fdiv.q f12, f11, f2 # C000 0000000000000000000000000000
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fsq f12, 96(x3)
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fsq f12, 96(x1)
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# sign injection -4 = 4
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# sign injection -4 = 4
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fsgnj.q f13, f12, f4 # 4001 0000000000000000000000000000
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fsgnj.q f13, f12, f4 # 4001 0000000000000000000000000000
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fsq f13, 112(x3)
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fsq f13, 112(x1)
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# sqrt(4) = 2
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# sqrt(4) = 2
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fsqrt.q f14, f13 # 4000 0000000000000000000000000000
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fsqrt.q f14, f13 # 4000 0000000000000000000000000000
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fsq f14, 128(x3)
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fsq f14, 128(x1)
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RVTEST_CODE_END
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RVTEST_CODE_END
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@ -94,12 +94,43 @@ RVMODEL_HALT
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RVTEST_DATA_BEGIN
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RVTEST_DATA_BEGIN
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.align 4
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.align 4
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rvtest_data:
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rvtest_data:
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test_dataset_0:
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.word 0xbabecafe
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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.word 0xecafebab
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test_dataset_0:
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test_dataset_1:
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test_dataset_1:
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RVTEST_DATA_END
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RVTEST_DATA_END
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@ -110,8 +141,14 @@ rvtest_sig_begin:
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signature_x1_1:
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signature_x1_1:
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.fill 8,8,0xdeadbeefdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.fill 8,8,0xdeadbeefdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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rvtest_sig_end:
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rvtest_sig_end:
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RVMODEL_DATA_END
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RVMODEL_DATA_END
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