Formatting.

pipelined/src/lsu/dtim.sv

@@ -1,10 +1,14 @@
 ///////////////////////////////////////////
 // dtim.sv
 //
-// Written: Ross Thompson ross1728@gmail.com January 30, 2022
+// Written: Ross Thompson ross1728@gmail.com 
-// Modified: 
+// Created: 30 January 2022
+// Modified: 18 January 2023
+//
+// Purpose: tightly integrated memory into the LSU.
+//
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
 //
-// Purpose: simple memory with bus or cache.
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -27,10 +31,10 @@
 
 module dtim(
   input logic 				 clk, 
-  input logic 				 ce,            // Chip Enable
+  input logic 				 FlushW,        
+  input logic 				 ce,            // Chip Enable.  0: Holds ReadDataWordM
   input logic [1:0] 		 MemRWM,        // Read/Write control
   input logic [`PA_BITS-1:0] AdrM,          // Execution stage memory address
-  input logic 				 FlushW, 
   input logic [`LLEN-1:0] 	 WriteDataM,    // Write data from IEU
   input logic [`LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
   output logic [`LLEN-1:0] 	 ReadDataWordM  // Read data before subword selection