mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Actually writes the correct data now on stores.
This commit is contained in:
Ross Thompson
parent
ee72178eec
commit
a82c4c99c2
@ -20,14 +20,14 @@ add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPa
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -105,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -213,13 +213,8 @@ add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext
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add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext
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add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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@ -240,19 +235,77 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HRDATAW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/StallW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
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||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW
|
||||||
|
add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW
|
||||||
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
|
||||||
@ -280,45 +333,40 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
|
|||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
|
add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
||||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
||||||
add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUTranslate
|
add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||||
add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
||||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr
|
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF
|
add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
add wave -noupdate -group ptwalker -divider data
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/MMUReadPTE
|
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
||||||
add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE
|
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
||||||
add wave -noupdate -expand -group ptwalker -divider data
|
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF
|
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
||||||
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM
|
add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
||||||
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
|
||||||
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||||
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
|
||||||
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
|
||||||
add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
|
||||||
add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
|
add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
|
|
||||||
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
|
|
||||||
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
|
|
||||||
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
|
|
||||||
add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/lsu/arbiter/MemAdrMtoLSU
|
|
||||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
|
||||||
@ -343,17 +391,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
|
|||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
|
||||||
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||||
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||||
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
||||||
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/MemAdrM
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/PCF
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 4} {16658 ns} 1} {{Cursor 4} {16655 ns} 0}
|
WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 6
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 189
|
configure wave -valuecolwidth 273
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
||||||
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
||||||
@ -366,4 +412,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {16565 ns} {16719 ns}
|
WaveRestoreZoom {57593 ns} {57969 ns}
|
||||||
|
|||||||
64
wally-pipelined/src/cache/dcache.sv
vendored
64
wally-pipelined/src/cache/dcache.sv
vendored
@ -73,12 +73,11 @@ module dcache
|
|||||||
|
|
||||||
|
|
||||||
logic SelAdrM;
|
logic SelAdrM;
|
||||||
logic [`PA_BITS-1:0] MemPAdrW;
|
|
||||||
logic [INDEXLEN-1:0] SRAMAdr;
|
logic [INDEXLEN-1:0] SRAMAdr;
|
||||||
logic [BLOCKLEN-1:0] SRAMWriteData;
|
logic [BLOCKLEN-1:0] SRAMWriteData;
|
||||||
logic [BLOCKLEN-1:0] DCacheMemWriteData;
|
logic [BLOCKLEN-1:0] DCacheMemWriteData;
|
||||||
logic SetValidM, ClearValidM, SetValidW, ClearValidW;
|
logic SetValidM, ClearValidM;
|
||||||
logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW;
|
logic SetDirtyM, ClearDirtyM;
|
||||||
logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0];
|
logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0];
|
||||||
logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
|
logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
|
||||||
logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0];
|
logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0];
|
||||||
@ -91,11 +90,11 @@ module dcache
|
|||||||
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
|
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
|
||||||
logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];
|
logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];
|
||||||
logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM;
|
logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM;
|
||||||
logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW;
|
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
|
||||||
logic [BLOCKLEN-1:0] FinalWriteDataWordsW;
|
logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
|
||||||
logic [LOGWPL:0] FetchCount, NextFetchCount;
|
logic [LOGWPL:0] FetchCount, NextFetchCount;
|
||||||
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
||||||
logic SelMemWriteDataM, SelMemWriteDataW;
|
logic SelMemWriteDataM;
|
||||||
logic [2:0] Funct3W;
|
logic [2:0] Funct3W;
|
||||||
|
|
||||||
logic SRAMWordWriteEnableM, SRAMWordWriteEnableW;
|
logic SRAMWordWriteEnableM, SRAMWordWriteEnableW;
|
||||||
@ -112,7 +111,6 @@ module dcache
|
|||||||
logic VictimDirty;
|
logic VictimDirty;
|
||||||
logic SelAMOWrite;
|
logic SelAMOWrite;
|
||||||
logic [6:0] Funct7W;
|
logic [6:0] Funct7W;
|
||||||
logic [INDEXLEN-1:0] AdrMuxOut;
|
|
||||||
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
||||||
|
|
||||||
logic [`PA_BITS-1:0] BasePAdrM;
|
logic [`PA_BITS-1:0] BasePAdrM;
|
||||||
@ -130,26 +128,12 @@ module dcache
|
|||||||
|
|
||||||
// data path
|
// data path
|
||||||
|
|
||||||
flopen #(`PA_BITS) MemPAdrWReg(.clk(clk),
|
|
||||||
.en(1'b1),
|
|
||||||
.d(MemPAdrM),
|
|
||||||
.q(MemPAdrW));
|
|
||||||
|
|
||||||
mux2 #(INDEXLEN)
|
mux2 #(INDEXLEN)
|
||||||
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.s(SelAdrM),
|
.s(SelAdrM),
|
||||||
.y(AdrMuxOut));
|
.y(SRAMAdr));
|
||||||
|
|
||||||
assign SRAMAdr = AdrMuxOut;
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
|
|
||||||
mux2 #(INDEXLEN)
|
|
||||||
SelAdrlMux2(.d0(AdrMuxOut),
|
|
||||||
.d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
|
||||||
.s(SRAMWordWriteEnableW),
|
|
||||||
.y(SRAMAdr));
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
|
|
||||||
oneHotDecoder #(LOGWPL)
|
oneHotDecoder #(LOGWPL)
|
||||||
oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
|
oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
|
||||||
@ -185,7 +169,7 @@ module dcache
|
|||||||
|
|
||||||
// the cache block candiate for eviction
|
// the cache block candiate for eviction
|
||||||
// *** this should be sharable with the read data muxing, but for now i'm doing the simple
|
// *** this should be sharable with the read data muxing, but for now i'm doing the simple
|
||||||
// thing and makign them separate.
|
// thing and making them separate.
|
||||||
assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0;
|
assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0;
|
||||||
assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way];
|
assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way];
|
||||||
assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0;
|
assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0;
|
||||||
@ -255,30 +239,20 @@ module dcache
|
|||||||
.q(ReadDataW));
|
.q(ReadDataW));
|
||||||
|
|
||||||
// write path
|
// write path
|
||||||
flopen #(`XLEN) WriteDataWReg(.clk(clk),
|
subwordwrite subwordwrite(.HRDATA(FinalReadDataWordM),
|
||||||
.en(~StallW),
|
|
||||||
.d(WriteDataM),
|
|
||||||
.q(WriteDataW));
|
|
||||||
|
|
||||||
flopr #(3) Funct3WReg(.clk(clk),
|
|
||||||
.reset(reset),
|
|
||||||
.d(Funct3M),
|
|
||||||
.q(Funct3W));
|
|
||||||
|
|
||||||
subwordwrite subwordwrite(.HRDATA(ReadDataW),
|
|
||||||
.HADDRD(MemPAdrM[2:0]),
|
.HADDRD(MemPAdrM[2:0]),
|
||||||
.HSIZED({Funct3W[2], 1'b0, Funct3W[1:0]}),
|
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
|
||||||
.HWDATAIN(WriteDataW),
|
.HWDATAIN(WriteDataM),
|
||||||
.HWDATA(FinalWriteDataW));
|
.HWDATA(FinalWriteDataM));
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`A_SUPPORTED) begin
|
if (`A_SUPPORTED) begin
|
||||||
logic [`XLEN-1:0] AMOResult;
|
logic [`XLEN-1:0] AMOResult;
|
||||||
amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W[1:0]),
|
amoalu amoalu(.srca(FinalReadDataWordM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
|
||||||
.result(AMOResult));
|
.result(AMOResult));
|
||||||
mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW);
|
mux2 #(`XLEN) wdmux(FinalWriteDataM, AMOResult, SelAMOWrite & AtomicM[1], FinalAMOWriteDataM);
|
||||||
end else
|
end else
|
||||||
assign FinalAMOWriteDataW = FinalWriteDataW;
|
assign FinalAMOWriteDataM = FinalWriteDataM;
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
@ -312,11 +286,11 @@ module dcache
|
|||||||
// mux between the CPU's write and the cache fetch.
|
// mux between the CPU's write and the cache fetch.
|
||||||
generate
|
generate
|
||||||
for(index = 0; index < WORDSPERLINE; index++) begin
|
for(index = 0; index < WORDSPERLINE; index++) begin
|
||||||
assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataW;
|
assign FinalWriteDataWordsM[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataM;
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW),
|
mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsM),
|
||||||
.d1(DCacheMemWriteData),
|
.d1(DCacheMemWriteData),
|
||||||
.s(SRAMBlockWriteEnableM),
|
.s(SRAMBlockWriteEnableM),
|
||||||
.y(SRAMWriteData));
|
.y(SRAMWriteData));
|
||||||
@ -387,11 +361,11 @@ module dcache
|
|||||||
|
|
||||||
assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
|
assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
|
||||||
|
|
||||||
flopr #(1+4+2)
|
flopr #(1)
|
||||||
SRAMWritePipeReg(.clk(clk),
|
SRAMWritePipeReg(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}),
|
.d({SRAMWordWriteEnableM}),
|
||||||
.q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW}));
|
.q({SRAMWordWriteEnableW}));
|
||||||
|
|
||||||
|
|
||||||
// fsm state regs
|
// fsm state regs
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user