From a8024eee26debd95df9c7c2a6a0ba4109bd3004d Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 6 Mar 2024 15:16:16 -0600
Subject: [PATCH] Revert "Updated subword misaligned."

This reverts commit 69d31d50e27199f105706172b5e2427f96689d3f.
---
 src/lsu/lsu.sv                                       |  2 +-
 src/lsu/subworddreadmisaligned.sv                    | 12 ++----------
 ...bwordwritemisaligned.sv => subwordwritedouble.sv} |  6 +++---
 3 files changed, 6 insertions(+), 14 deletions(-)
 rename src/lsu/{subwordwritemisaligned.sv => subwordwritedouble.sv} (97%)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 0af655dbf..8e827292f 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -425,7 +425,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   if(MISALIGN_SUPPORT) begin
     subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
       .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
-    subwordwritemisaligned #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
+    subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
   end else begin
     subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
       .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
diff --git a/src/lsu/subworddreadmisaligned.sv b/src/lsu/subworddreadmisaligned.sv
index 1e179dbc3..fe96844f3 100644
--- a/src/lsu/subworddreadmisaligned.sv
+++ b/src/lsu/subworddreadmisaligned.sv
@@ -38,7 +38,6 @@ module subwordreadmisaligned #(parameter LLEN)
    output logic [LLEN-1:0]  ReadDataM
 );
 
-  logic [LLEN*2-1:0]        ReadDataAlignedM;
   logic [7:0]               ByteM; 
   logic [15:0]              HalfwordM;
   logic [31:0]              WordM;
@@ -65,20 +64,13 @@ module subwordreadmisaligned #(parameter LLEN)
       default: LengthM = 5'd8;
     endcase
 
+  logic [LLEN*2-1:0]        ReadDataAlignedM;
   assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8);
   
   assign ByteM = ReadDataAlignedM[7:0];
   assign HalfwordM = ReadDataAlignedM[15:0];
   assign WordM = ReadDataAlignedM[31:0];
 
-  logic [LLEN-1:0]          lb, lh_flh, lw_flw, ld_fld, lbu, lbu_flq, lhu, lwu;
-
-  assign lb      = {{LLEN-8{ByteM[7]}}, ByteM};
-  assign lh_flh  = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};;
-  assign lw_flw  = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};
-  //assign ld_fld  = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};
-  
-
   if (LLEN == 128) begin:swrmux
     logic [63:0] DblWordM;
     logic [127:0] QdWordM;
@@ -128,7 +120,7 @@ module subwordreadmisaligned #(parameter LLEN)
       3'b001:  ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};               // lh/flh
       3'b010:  ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};                       // lw/flw
 
-      //3'b011:  ReadDataM = WordM[LLEN-1:0];                                                        // fld
+      3'b011:  ReadDataM = WordM[LLEN-1:0];                                                        // fld
 
       3'b100:  ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]};                                           // lbu
       3'b101:  ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]};                                     // lhu
diff --git a/src/lsu/subwordwritemisaligned.sv b/src/lsu/subwordwritedouble.sv
similarity index 97%
rename from src/lsu/subwordwritemisaligned.sv
rename to src/lsu/subwordwritedouble.sv
index dd82ffa19..eb62aa106 100644
--- a/src/lsu/subwordwritemisaligned.sv
+++ b/src/lsu/subwordwritedouble.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// subwordwritemisaligned.sv
+// subwordwrite.sv
 //
 // Written: David_Harris@hmc.edu
 // Created: 9 January 2021
@@ -28,7 +28,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module subwordwritemisaligned #(parameter LLEN) (
+module subwordwritedouble #(parameter LLEN) (
   input logic [2:0]         LSUFunct3M,
   input logic [2:0]         PAdrM,
   input logic               FpLoadStoreM, 
@@ -38,7 +38,7 @@ module subwordwritemisaligned #(parameter LLEN) (
   output logic [LLEN*2-1:0] LittleEndianWriteDataM
 );
 
-  // *** RT: This is logic is duplicated in subwordreadmisaligned. Merge the two.
+  // *** RT: This is logic is duplicated in subwordreaddouble. Merge the two.
   logic [4:0]               PAdrSwap;
   logic [4:0]               BigEndianPAdr;
   logic [4:0]               LengthM;