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Added comments to finish store delay stall removal.

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Rose Thompson 2023-12-13 20:35:13 -06:00
parent 9cf6b1fdeb
commit a7f0aaa722
1 changed files with 2 additions and 2 deletions
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src/ieu/controller.sv
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@ -427,7 +427,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
// the synchronous DTIM cannot read immediately after write
// a cache cannot read or write immediately after a write
// atomic operations are also detected as MemRWD[1]
//assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
//assign StoreStallD = (MemRWE[0] | (|CMOpE)) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | (|CMOpD)));
// *** RT: Remove this after updating the cache.
// *** RT: Check that atomic after atomic works correctly.
assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
endmodule