From a7dd2eff016e77ba522623cf22f2734bee340209 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 12:29:02 -0600 Subject: [PATCH] Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa. --- sim/rv64gc_CacheSim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 87616edd0..9de361237 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -65,7 +65,7 @@ def main(): parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites") parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio") parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations") - parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") + parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator") args = parser.parse_args() simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1" testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"