diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 62e9eca65..e558735de 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -80,6 +80,7 @@ module controller( logic subD, sraD, sltD, sltuD; logic BranchTakenE; logic zeroE, ltE, ltuE; + logic unused; // Main Instruction Decoder @@ -100,7 +101,7 @@ module controller( 7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64) ControlsD = 21'b1_000_00_00_000_0_10_0_0_1_0_0_0_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64) - ControlsD = 21'b1_000_00_00_100_0_00_0_0_1_0_0_1_0; // Multiply/Divide + ControlsD = 21'b1_000_00_00_100_0_00_0_0_1_0_0_1_0; // W-type Multiply/Divide else ControlsD = 21'b0_000_00_00_000_0_00_0_0_0_0_0_0_1; // non-implemented instruction 7'b1100011: ControlsD = 21'b0_010_00_00_000_1_01_0_0_0_0_0_0_0; // beq @@ -128,7 +129,7 @@ module controller( assign IllegalBaseInstrFaultD = ControlsD[0]; assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRWriteD, - PrivilegedD, MulDivD} = ControlsD[20:1] & ~IllegalIEUInstrFaultD; + PrivilegedD, MulDivD, unused} = ControlsD & ~IllegalIEUInstrFaultD; // *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions // ALU Decoding *** should move to ALU for better modularity diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv new file mode 100644 index 000000000..2fee66e65 --- /dev/null +++ b/wally-pipelined/src/muldiv/mul.sv @@ -0,0 +1,77 @@ +/////////////////////////////////////////// +// mul.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Multiply instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module mul ( + // Execute Stage interface + input logic [`XLEN-1:0] SrcAE, SrcBE, + input logic [2:0] Funct3E, + output logic [`XLEN*2-1:0] ProdE +); + + // Number systems + // Let A' = sum(i=0, XLEN-2, A[i]*2^i) + // Unsigned: A = A' + A[XLEN-1]*2^(XLEN-1) + // Signed: A = A' - A[XLEN-1]*2^(XLEN-1) + + // Multiplication: A*B + // Let P' = A' * B' + // PA = (A' * B[XLEN-1]) + // PB = (B' * A[XLEN-1]) + // PP = A[XLEN-1] * B[XLEN-1] + // Signed * Signed = P' + (-PA - PB)*2^(XLEN-1) + PP*2^(2XLEN-2) + // Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2) + // Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2) + + logic [`XLEN*2-1:0] PP1, PP2, PP3, PP4; + logic [`XLEN*2-1:0] Pprime; + logic [`XLEN-2:0] PA, PB; + logic PP; + logic MULH, MULHSU, MULHU; + + // portions of product + assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]}; + assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0]; + assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0]; + assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1]; + + // flavor of multiplication + assign MULH = (Funct3E == 2'b01); + assign MULHSU = (Funct3E == 2'b10); + assign MULHU = (Funct3E == 2'b11); + + // Handle signs + assign PP1 = Pprime; // same for all flavors + assign PP2 = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}}; + assign PP3 = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}}; + always_comb + if (MULH) PP4 = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}}; + else if (MULHSU) PP4 = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}}; + else PP4 = {1'b0, PP, {(`XLEN*2-2){1'b0}}}; + + assign ProdE = PP1 + PP2 + PP3 + PP4; //SrcAE * SrcBE; + endmodule + diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index 75b63e665..3cd13ab2d 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -31,21 +31,48 @@ module muldiv ( input logic [31:0] InstrD, // Execute Stage interface input logic [`XLEN-1:0] SrcAE, SrcBE, + input logic [2:0] Funct3E, input logic MulDivE, W64E, // Writeback stage output logic [`XLEN-1:0] MulDivResultW, // hazards - input logic FlushM, FlushW // ***fewer? + input logic FlushM, FlushW ); - - logic [`XLEN*2-1:0] ProdE; - logic [`XLEN-1:0] MulDivResultE, MulDivResultM; - assign ProdE = SrcAE * SrcBE; - assign MulDivResultE = ProdE[`XLEN-1:0]; + generate + if (`M_SUPPORTED) begin + logic [`XLEN-1:0] MulDivResultE, MulDivResultM; + logic [`XLEN-1:0] PrelimResultE; + logic [`XLEN-1:0] QuotE, RemE; + logic [`XLEN*2-1:0] ProdE; - floprc #(`XLEN) MulDivResultMReg(clk, reset, FlushM, MulDivResultE, MulDivResultM); - floprc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, MulDivResultM, MulDivResultW); + mul mul(.*); + // Select result + always_comb + case (Funct3E) + 3'b000: PrelimResultE = ProdE[`XLEN-1:0]; + 3'b001: PrelimResultE = ProdE[`XLEN*2-1:`XLEN]; + 3'b010: PrelimResultE = ProdE[`XLEN*2-1:`XLEN]; + 3'b011: PrelimResultE = ProdE[`XLEN*2-1:`XLEN]; + 3'b100: PrelimResultE = QuotE; + 3'b101: PrelimResultE = QuotE; + 3'b110: PrelimResultE = RemE; + 3'b111: PrelimResultE = RemE; + endcase + + // Handle sign extension for W-type instructions + if (`XLEN == 64) begin // RV64 has W-type instructions + assign MulDivResultE = W64E ? {{32{PrelimResultE[31]}}, PrelimResultE[31:0]} : PrelimResultE; + end else begin // RV32 has no W-type instructions + assign MulDivResultE = PrelimResultE; + end + + floprc #(`XLEN) MulDivResultMReg(clk, reset, FlushM, MulDivResultE, MulDivResultM); + floprc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, MulDivResultM, MulDivResultW); + end else begin // no M instructions supported + assign MulDivResultW = 0; + end + endgenerate endmodule diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 5b3b68072..ce36c0364 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -38,7 +38,19 @@ module testbench(); logic [31:0] InstrW; logic [`XLEN-1:0] meminit; string tests64m[] = '{ - "rv64m/I-MUL-01", "3000" + "rv64m/I-MUL-01", "3000", + "rv64m/I-MULH-01", "3000", + "rv64m/I-MULHSU-01", "3000", + "rv64m/I-MULHU-01", "3000", + "rv64m/I-MULW-01", "3000" +// "rv64m/I-DIV-01", "3000", +// "rv64m/I-DIVU-01", "3000", + // "rv64m/I-DIVUW-01", "3000", + // "rv64m/I-DIVW-01", "3000", +// "rv64m/I-REM-01", "3000", +// "rv64m/I-REMU-01", "3000", +// "rv64m/I-REMUW-01", "3000", +// "rv64m/I-REMW-01", "3000" }; string tests64ic[] = '{ @@ -176,7 +188,14 @@ string tests64iNOc[] = { }; string tests32m[] = '{ - "rv32m/I-MUL-01", "3000" + "rv32m/I-MUL-01", "2000", + "rv32m/I-MULH-01", "2000", + "rv32m/I-MULHSU-01", "2000", + "rv32m/I-MULHU-01", "2000" +// "rv32m/I-DIV-01", "2000", +// "rv32m/I-DIVU-01", "2000", +// "rv32m/I-REM-01", "2000", +// "rv32m/I-REMU-01", "2000" }; string tests32ic[] = '{ // "rv32ic/WALLY-C-ADHOC-01", "2000", @@ -277,12 +296,12 @@ string tests32i[] = { "rv32i/WALLY-BLT", "4000", "rv32i/WALLY-BGE", "4000 ", "rv32i/WALLY-BGEU", "4000 ", - "rv64i/WALLY-CSRRW", "3000", - "rv64i/WALLY-CSRRS", "3000", - "rv64i/WALLY-CSRRC", "4000", - "rv64i/WALLY-CSRRWI", "3000", - "rv64i/WALLY-CSRRSI", "3000", - "rv64i/WALLY-CSRRCI", "3000" + "rv32i/WALLY-CSRRW", "3000", + "rv32i/WALLY-CSRRS", "3000", + "rv32i/WALLY-CSRRC", "4000", + "rv32i/WALLY-CSRRWI", "3000", + "rv32i/WALLY-CSRRSI", "3000", + "rv32i/WALLY-CSRRCI", "3000" }; string tests[]; @@ -305,7 +324,7 @@ string tests32i[] = { tests = {tests64i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; - if (`M_SUPPORTED % 2 == 1) tests = {tests, tests64m}; + if (`M_SUPPORTED % 2 == 1) tests = {tests64m, tests}; end else begin // RV32 tests = {tests32i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; @@ -523,10 +542,10 @@ module instrNameDecTB( else if (funct7 == 7'b0000001) name = "MULHSU"; else name = "ILLEGAL"; 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; - else if (funct7 == 7'b0000001) name = "DIV"; + else if (funct7 == 7'b0000001) name = "MULHU"; else name = "ILLEGAL"; 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; - else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0000001) name = "DIV"; else name = "ILLEGAL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; else if (funct7 == 7'b0000001) name = "DIVU";