Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Possible fix for interrupt during a floating point divide.

Browse Source
This commit is contained in:
Ross Thompson 2022-10-18 15:04:21 -05:00
parent 2c80c2b35f
commit a7ae593a68
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/hazard/hazard.sv
View File

@ -69,7 +69,7 @@ module hazard(
assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)) | FDivBusyE; assign StallMCause = ((wfiM | FDivBusyE) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
assign StallWCause = LSUStallM | IFUStallF; assign StallWCause = LSUStallM | IFUStallF;
assign #1 StallF = StallFCause | StallD; assign #1 StallF = StallFCause | StallD;