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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed unused hardware from alignment.
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@ -65,22 +65,20 @@ module align import cvw::*; #(parameter cvw_t P) (
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logic SpillM;
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logic SpillM;
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logic SelSpillM;
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logic SelSpillM;
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logic SpillSaveM;
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logic SpillSaveM;
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logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
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logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
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logic ValidMisalignedM, MisalignedM;
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logic ValidMisalignedM, MisalignedM;
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logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
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logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
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logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
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logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
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logic [P.XLEN-1:0] IEUAdrIncrementM;
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logic [P.XLEN-1:0] IEUAdrIncrementM;
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logic [(P.LLEN-1)*2/8:0] ByteMaskSaveM;
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logic HalfMisalignedM, WordMisalignedM;
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logic [(P.LLEN-1)*2/8:0] ByteMaskMuxM;
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logic HalfMisalignedM, WordMisalignedM;
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logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
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logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
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logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
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logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
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logic HalfSpillM, WordSpillM;
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logic HalfSpillM, WordSpillM;
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logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
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logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
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logic [$clog2(LLENINBYTES)+2:0] ShiftAmount;
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logic [$clog2(LLENINBYTES)+2:0] ShiftAmount;
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logic ValidAccess;
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logic ValidAccess;
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/* verilator lint_off WIDTHEXPAND */
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/* verilator lint_off WIDTHEXPAND */
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assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
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assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
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@ -179,11 +177,9 @@ module align import cvw::*; #(parameter cvw_t P) (
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assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
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assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
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assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
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assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
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mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
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mux3 #(2*P.LLEN/8) bytemaskspillmux({ByteMaskExtendedM, ByteMaskM}, // no spill
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{{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
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{{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
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{{{P.LLEN/8}{1'b0}}, ByteMaskMuxM[P.LLEN*2/8-1:P.LLEN/8]}, // spill, second half
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{{{P.LLEN/8}{1'b0}}, ByteMaskExtendedM}, // spill, second half
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{SelSpillM, SelSpillE}, ByteMaskSpillM);
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{SelSpillM, SelSpillE}, ByteMaskSpillM);
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flopenr #(P.LLEN*2/8) bytemaskreg(clk, reset, SpillSaveM, {ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM);
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mux2 #(P.LLEN*2/8) bytemasksavemux({ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM, SelSpillM, ByteMaskMuxM);
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endmodule
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endmodule
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