From a66bd9008c18b7bd1ce574808d3bef2161e37386 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Fri, 22 Jan 2021 21:14:45 -0500 Subject: [PATCH] slightly more info on errors, add instruction decoding --- wally-pipelined/src/testbench-busybear.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/src/testbench-busybear.sv index 1de8ca9c9..2ff003a8f 100644 --- a/wally-pipelined/src/testbench-busybear.sv +++ b/wally-pipelined/src/testbench-busybear.sv @@ -81,7 +81,8 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]); // check things! if (rf[j*64+63 -: 64] != rfExpected[j]) begin - $display("rf[%i] does not equal rf expected: %x, %x", j, rf[j*64+63 -: 64], rfExpected[j]); + $display("%t ps: rf[%i] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]); + $stop; end end end @@ -101,10 +102,19 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); //check things! if (PCF != pcExpected) begin - $display("PC does not equal PC expected: %x, %x", PCF, pcExpected); + $display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected); + $stop; end end + // Track names of instructions + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + instrNameDecTB dec(InstrF, InstrFName); + instrTrackerTB #(XLEN) it(clk, reset, dut.dp.FlushE, + dut.dp.InstrDecompD, dut.dp.InstrE, + dut.dp.InstrM, InstrW, + InstrDName, InstrEName, InstrMName, InstrWName); // generate clock to sequence tests always