From a62211bad1b121a1e4ca34ca8a64772ccab896fd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Jun 2023 11:56:59 -0700 Subject: [PATCH] Gated inputs to BMU when inactive to save power and simulation time --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/bitmanipalu.sv | 14 ++++++++++---- src/ieu/bmu/bmuctrl.sv | 5 +++-- src/ieu/controller.sv | 4 +++- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 6 ++++-- 6 files changed, 24 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 43df83b60..1114245e9 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -38,6 +38,7 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // For BMU decoding input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + input logic BMUActiveE, // Bit manipulation instruction being executed output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -88,7 +89,7 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, + bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE, .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 228b23132..96076cc84 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -38,6 +38,7 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic LT, // less than flag input logic LTU, // less than unsigned flag input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + input logic BMUActiveE, // Bit manipulation instruction being executed input logic [WIDTH-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions @@ -51,13 +52,18 @@ module bitmanipalu #(parameter WIDTH=32) ( logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal + logic [WIDTH-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity + + // gate data inputs to BMU to only operate when BSelect[1] indicates BMU is in use + assign ABMU = A & {WIDTH{BMUActiveE}}; + assign BBMU = B & {WIDTH{BMUActiveE}}; // Extract control signals from bitmanip ALUControl. assign {Mask, PreShift} = BALUControl[1:0]; // Mask Generation Mux if (`ZBS_SUPPORTED) begin: zbsdec - decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB); + decoder #($clog2(WIDTH)) maskgen(BBMU[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; @@ -75,17 +81,17 @@ module bitmanipalu #(parameter WIDTH=32) ( // Bit reverse needed for some ZBB, ZBC instructions if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse - bitreverse #(WIDTH) brA(.A, .RevA); + bitreverse #(WIDTH) brA(.A(ABMU), .RevA); end // ZBC Unit if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); + zbc #(WIDTH) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); end else assign ZBCResult = 0; // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); + zbb #(WIDTH) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Result Select Mux diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ad46ab728..59a8e4a16 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -46,7 +46,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute - output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage + output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage + output logic BMUActiveE // Bit manipulation instruction being executed ); logic [6:0] OpD; // Opcode in Decode stage @@ -174,5 +175,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); // BMU Execute stage pipieline control register - flopenrc #(9) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE}); + flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); endmodule diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 8839b9cad..c47eb6799 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -58,6 +58,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage + output logic BMUActiveE, // Bit manipulation instruction being executed // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -253,7 +254,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( bmuctrl #(P) bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, - .ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE); + .ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE); if (P.ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -282,6 +283,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign BSelectD = 2'b00; assign ZBBSelectE = 3'b000; assign BALUControlE = 3'b0; + assign BMUActiveE = 1'b0; end // Fences diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 40a72926e..e48bd2c38 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -48,6 +48,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage + input logic BMUActiveE, // Bit manipulation instruction being executed output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [P.XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -112,7 +113,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE); + alu #(P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 8e22fd864..7dc7c5c97 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -93,12 +93,14 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic MemReadE, CSRReadE; // Load, CSRRead instruction logic BranchSignedE; // Branch does signed comparison on operands logic MDUE; // Multiply/divide instruction + logic BMUActiveE; // Bit manipulation instruction being executed controller #(P) c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); @@ -106,7 +108,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( datapath #(P) dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);