Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added artya7 device tree.

Browse Source
This commit is contained in:
Ross Thompson 2023-07-17 16:01:02 -05:00
parent f872be6fc3
commit a5f75d568b
1 changed files with 76 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
linux/devicetree/wally-artya7.dts Normal file
View File

@ -0,0 +1,76 @@
/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "wally-virt";
model = "wally-virt,qemu";
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro";
stdout-path = "/soc/uart@10000000";
};
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x08000000>;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0xE4E1C0>;
timebase-frequency = <0xE4E1C0>;
cpu@0 {
phandle = <0x01>;
device_type = "cpu";
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv48";
interrupt-controller {
#interrupt-cells = <0x01>;
interrupt-controller;
compatible = "riscv,cpu-intc";
phandle = <0x02>;
};
};
};
soc {
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "simple-bus";
ranges;
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0xE4E1C0>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
plic@c000000 {
phandle = <0x03>;
riscv,ndev = <0x35>;
reg = <0x00 0xc000000 0x00 0x210000>;
interrupts-extended = <0x02 0x0b 0x02 0x09>;
interrupt-controller;
compatible = "sifive,plic-1.0.0\0riscv,plic0";
#interrupt-cells = <0x01>;
#address-cells = <0x00>;
};
clint@2000000 {
interrupts-extended = <0x02 0x03 0x02 0x07>;
reg = <0x00 0x2000000 0x00 0x10000>;
compatible = "sifive,clint0\0riscv,clint0";
};
};
};