From a5dc09c97f42ae89c98f2cb1b006cedf715fa475 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 21 Dec 2022 13:57:28 -0800
Subject: [PATCH] Added assertion about atomics needing caches

---
 pipelined/testbench/testbench.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 030f348d5..e67ab1d32 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -484,6 +484,7 @@ module riscvassertions;
     assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
     assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
   end