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More cache cleanup.

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This commit is contained in:
Ross Thompson 2022-02-13 12:38:39 -06:00
parent dd944265aa
commit a5ad4331ec
3 changed files with 3 additions and 6 deletions
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2
pipelined/src/cache/cache.sv vendored
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@ -151,13 +151,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Flush address and way generation during flush // Flush address and way generation during flush
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// *** this could be improved. reduce to a single adder of size $clog2(numway+numlines)
assign ResetOrFlushAdr = reset | FlushAdrCntRst; assign ResetOrFlushAdr = reset | FlushAdrCntRst;
flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn),
.d(FlushAdrP1), .q(FlushAdr)); .d(FlushAdrP1), .q(FlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrP1 = FlushAdr + 1'b1;
assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]);
assign ResetOrFlushWay = reset | FlushWayCntRst; assign ResetOrFlushWay = reset | FlushWayCntRst;
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));

3
pipelined/src/cache/cachefsm.sv vendored
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@ -147,8 +147,7 @@ module cachefsm
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
else NextState = STATE_MISS_READ_WORD_DELAY; else NextState = STATE_MISS_READ_WORD_DELAY;
STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;

4
pipelined/src/cache/cacheway.sv vendored
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@ -88,9 +88,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn));
// AND portion of distributed tag multiplexer // AND portion of distributed tag multiplexer
assign SelTag = SelFlush ? FlushWay : VictimWay; mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux
assign VictimDirtyWay = SelTag & Dirty & Valid; assign VictimDirtyWay = SelTag & Dirty & Valid;
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Data Array // Data Array
@ -106,7 +107,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
end end
// AND portion of distributed read multiplexers // AND portion of distributed read multiplexers
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux. assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.