From a5a89e58a8d6b73c3195f2c9924f1d9deddb57ca Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jan 2022 18:22:30 +0000 Subject: [PATCH] Fixed unpacking bug; regression runs again --- examples/verilog/fulladder/fulladder.sv | 52 +++++++++++++++++++ examples/verilog/fulladder/fulladder.tv | 8 +++ pipelined/src/fpu/unpacking.sv | 20 +++++--- pipelined/src/generic/decoder.sv | 37 ++++++++++++++ pipelined/src/generic/priorityonehot.sv | 47 +++++++++++++++++ pipelined/src/generic/prioritythermometer.sv | 54 ++++++++++++++++++++ 6 files changed, 212 insertions(+), 6 deletions(-) create mode 100644 examples/verilog/fulladder/fulladder.sv create mode 100644 examples/verilog/fulladder/fulladder.tv create mode 100644 pipelined/src/generic/decoder.sv create mode 100644 pipelined/src/generic/priorityonehot.sv create mode 100644 pipelined/src/generic/prioritythermometer.sv diff --git a/examples/verilog/fulladder/fulladder.sv b/examples/verilog/fulladder/fulladder.sv new file mode 100644 index 000000000..4122b4978 --- /dev/null +++ b/examples/verilog/fulladder/fulladder.sv @@ -0,0 +1,52 @@ +module testbench(); + logic clk, reset; + logic a, b, c, s, cout, sexpected, coutexpected; + logic [31:0] vectornum, errors; + logic [4:0] testvectors[10000:0]; + + // instantiate device under test + fulladder dut(a, b, c, s, cout); + + // generate clock + always + begin + clk = 1; #5; clk = 0; #5; + end + + // at start of test, load vectors and pulse reset + initial + begin + $readmemb("fulladder.tv", testvectors); + vectornum = 0; errors = 0; + reset = 1; #22; reset = 0; + end + + // apply test vectors on rising edge of clk + always @(posedge clk) + begin + #1; {a, b, c, coutexpected, sexpected} = testvectors[vectornum]; + end + + // check results on falling edge of clk + always @(negedge clk) + if (~reset) begin // skip during reset + if (s !== sexpected | cout !== coutexpected) begin // check result + $display("Error: inputs = %b", {a, b, c}); + $display(" outputs cout s = %b%b (%b%b expected)",cout, s, coutexpected, sexpected); + errors = errors + 1; + end + vectornum = vectornum + 1; + if (testvectors[vectornum] === 5'bx) begin + $display("%d tests completed with %d errors", + vectornum, errors); + $stop; + end + end +endmodule + +module fulladder(input logic a, b, c, + output logic s, cout); + + assign s = a ^ b ^ c; + assign cout = (a & b) | (a & c) | (b & c); +endmodule diff --git a/examples/verilog/fulladder/fulladder.tv b/examples/verilog/fulladder/fulladder.tv new file mode 100644 index 000000000..960acebb6 --- /dev/null +++ b/examples/verilog/fulladder/fulladder.tv @@ -0,0 +1,8 @@ +000_00 +001_01 +010_01 +011_10 +100_01 +101_10 +110_10 +111_11 diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index e184fbc21..f64901a7c 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -1,3 +1,5 @@ +`include "wally-config.vh" + module unpacking ( input logic [63:0] X, Y, Z, input logic FmtE, @@ -23,9 +25,15 @@ module unpacking ( logic XDoubleNaN, YDoubleNaN, ZDoubleNaN; // Determine if number is NaN as double precision to check single precision NaN boxing - assign XDoubleNaN = &X[62:52] & |X[51:0]; - assign YDoubleNaN = &Y[62:52] & |Y[51:0]; - assign ZDoubleNaN = &Z[62:52] & |Z[51:0]; + if (`XLEN==32) begin + assign XDoubleNaN = 1; + assign YDoubleNaN = 1; + assign ZDoubleNaN = 1; + end else begin + assign XDoubleNaN = &X[62:52] & |X[51:0]; + assign YDoubleNaN = &Y[62:52] & |Y[51:0]; + assign ZDoubleNaN = &Z[62:52] & |Z[51:0]; + end assign XSgnE = FmtE ? X[63] : X[31]; assign YSgnE = FmtE ? Y[63] : Y[31]; @@ -62,9 +70,9 @@ module unpacking ( assign XNormE = ~(XExpMaxE|XExpZero); // force single precision input to be a NaN if it isn't properly Nan Boxed - assign XNaNE = XExpMaxE & ~XFracZero | ~FmtE & ~XDoubleNan; - assign YNaNE = YExpMaxE & ~YFracZero | ~FmtE & ~YDoubleNan; - assign ZNaNE = ZExpMaxE & ~ZFracZero | ~FmtE & ~ZDoubleNan; + assign XNaNE = XExpMaxE & ~XFracZero | ~FmtE & ~XDoubleNaN; + assign YNaNE = YExpMaxE & ~YFracZero | ~FmtE & ~YDoubleNaN; + assign ZNaNE = ZExpMaxE & ~ZFracZero | ~FmtE & ~ZDoubleNaN; assign XSNaNE = XNaNE&~XFracE[51]; assign YSNaNE = YNaNE&~YFracE[51]; diff --git a/pipelined/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv new file mode 100644 index 000000000..7fa4f8eda --- /dev/null +++ b/pipelined/src/generic/decoder.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// decoder.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 +// Modified: +// +// Purpose: Binary encoding to one-hot decoder +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module decoder #(parameter BINARY_BITS = 3) ( + input logic [BINARY_BITS-1:0] binary, + output logic [(2**BINARY_BITS)-1:0] onehot +); + + // *** Double check whether this synthesizes as expected + // -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists + assign onehot = 1 << binary; + +endmodule diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv new file mode 100644 index 000000000..bf9d041be --- /dev/null +++ b/pipelined/src/generic/priorityonehot.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// priorityonehot.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 +// Modified: Teo Ene 15 Apr 2021: +// Temporarily removed paramterized priority encoder for non-parameterized one +// To get synthesis working quickly +// Kmacsaigoren@hmc.edu 28 May 2021: +// Added working version of parameterized priority encoder. +// David_Harris@Hmc.edu switched to one-hot output +// +// Purpose: Priority circuit producing a 1 in the output in the column where +// the least significant 1 appears in the input. +// +// Example: msb lsb +// in 01011101010100000 +// out 00000000000100000 +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module priorityonehot #(parameter N = 8) ( + input logic [N-1:0] a, + output logic [N-1:0] y +); + logic [N-1:0] nolower; + + // create thermometer code mask + prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower)); + assign y = a & nolower; +endmodule diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv new file mode 100644 index 000000000..78f00d88e --- /dev/null +++ b/pipelined/src/generic/prioritythermometer.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// prioritythermometer.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 +// David_Harris@Hmc.edu switched to one-hot output +// +// Purpose: Priority circuit producing a thermometer code output. +// with 1's in all the least signficant bits of the output +// until the column where the least significant 1 occurs in the input. +// +// Example: msb lsb +// in 01011101010100000 +// out 00000000000011111 +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +/* verilator lint_off UNOPTFLAT */ + +module prioritythermometer #(parameter N = 8) ( + input logic [N-1:0] a, + output logic [N-1:0] y +); + +// Carefully crafted so design compiler will synthesize into a fast tree structure +// Rather than linear. + + // create thermometer code mask + genvar i; + assign y[0] = ~a[0]; + for (i=1; i