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https://github.com/openhwgroup/cvw
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Updated regression to avoid iter-elf
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5
Makefile
5
Makefile
@ -8,7 +8,7 @@ all:
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make riscof
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make testfloat
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# make verify
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# make coverage
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make coverage
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# make benchmarks
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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@ -35,6 +35,9 @@ coremark:
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embench:
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cd ${WALLY}/benchmarks/embench; make; make run
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coverage:
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make -C tests/coverage
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clean:
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make clean -C sim
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@ -284,7 +284,7 @@ def addTests(tests, sim):
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def addLockstepTestsByDir(dir, config, sim):
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sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
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cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
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cmdPrefix="wsim --lockstep --sim " + sim + " " + coverStr + " " + config
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for file in os.listdir(dir):
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if file.endswith(".elf"):
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fullfile = os.path.join(dir, file)
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@ -387,14 +387,6 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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addTests(tests64gc_fp, coveragesim)
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elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
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addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim)
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#sim_log = WALLY + "/sim/questa/logs/fcov.log"
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#tc = TestCase(
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# name="lockstep_functcov",
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# variant="rv64gc",
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# cmd="iterelf " + WALLY + "/tests/functcov/rv64/I > " + sim_log,
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# grepstr="SUCCESS! All tests ran without failures",
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# grepfile = sim_log)
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#configs.append(tc)
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elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
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addTests(tests64gc_nofp, coveragesim)
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if (args.fp):
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@ -409,23 +401,8 @@ else:
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# run derivative configurations and lockstep tests in nightly regression
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if (args.nightly):
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sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log"
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tc = TestCase(
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name="lockstep_coverage",
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variant="rv64gc",
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cmd="iterelf " + WALLY + "/tests/coverage > " + sim_log,
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grepstr="SUCCESS! All tests ran without failures",
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grepfile = sim_log)
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configs.append(tc)
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sim_log = WALLY + "/sim/questa/logs/lockstep_wally-riscv-arch-test.log"
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tc = TestCase(
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name="lockstep_wally-riscv-arch-test",
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variant="rv64gc",
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cmd="iterelf " + WALLY + "/tests/riscof/work/wally-riscv-arch-test/rv64i_m > " + sim_log,
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grepstr="SUCCESS! All tests ran without failures",
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grepfile = sim_log)
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configs.append(tc)
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addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa")
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addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa")
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addTests(derivconfigtests, defaultsim)
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# testfloat tests
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