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Ross Thompson 2023-01-18 17:56:47 -06:00
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pipelined/src/lsu/amoalu.sv
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@ -1,11 +1,14 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// amoalu.sv // amoalu.sv
// //
// Written: David_Harris@hmc.edu 10 March 2021 // Written: David_Harris@hmc.edu
// Modified: // Created: 10 March 2021
// Modified: 18 January 2023
// //
// Purpose: Performs AMO operations // Purpose: Performs AMO operations
// //
// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -26,13 +29,12 @@
`include "wally-config.vh" `include "wally-config.vh"
// *** this should probably be moved into the LSU because it is instantiated in the D$
module amoalu ( module amoalu (
input logic [`XLEN-1:0] srca, srcb, input logic [`XLEN-1:0] srca, // LSU's ReadData *** may want to change signal names.
input logic [6:0] funct, input logic [`XLEN-1:0] srcb, // LSU's WriteData
input logic [1:0] width, input logic [6:0] funct, // ALU Operation
output logic [`XLEN-1:0] result input logic [1:0] width, // Memoy access width
output logic [`XLEN-1:0] result // ALU output
); );
logic [`XLEN-1:0] a, b, y; logic [`XLEN-1:0] a, b, y;