From 92accfb1a64af1263b024deb7029a31ea257db8d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Oct 2022 15:05:33 -0500 Subject: [PATCH] Updated uart settings and fpga wave config. --- fpga/generator/wave_config.wcfg | 531 ++++++++++++++++++++++++++- pipelined/src/uncore/uartPC16550D.sv | 4 +- 2 files changed, 520 insertions(+), 15 deletions(-) diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg index 306ec0a76..1d64470ac 100644 --- a/fpga/generator/wave_config.wcfg +++ b/fpga/generator/wave_config.wcfg @@ -3,22 +3,29 @@ - + - - - + + + - + - + + + + + + + + FullPathName @@ -36,6 +43,31 @@ true STYLE_DIGITAL + + rd + label + UNSIGNEDDECRADIX + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + [7] + [7] + + FullPathName wallypipelinedsoc/core/InstrValidM @@ -50,10 +82,17 @@ true STYLE_DIGITAL + + FullPathName + wallypipelinedsoc/core/lsu/ReadDataM[63:0] + ReadDataM[63:0] + HEXRADIX + true + STYLE_DIGITAL + CPU to LSU label - FullPathName wallypipelinedsoc/core/IEUAdrM[63:0] @@ -79,6 +118,30 @@ STYLE_DIGITAL + + FullPathName + wallypipelinedsoc/core/IEUAdrM[63:0] + IEUAdrM[63:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/MemRWM[1:0] + MemRWM[1:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/lsu/WriteDataM[63:0] + WriteDataM[63:0] + HEXRADIX + true + STYLE_DIGITAL + xIP label @@ -133,39 +196,59 @@ LSU to Bus label - + FullPathName wallypipelinedsoc/core/lsu/LSUHADDR[31:0] LSUHADDR[31:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/LSUHBURST[2:0] LSUHBURST[2:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/LSUHREADY LSUHREADY + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/LSUHSIZE[1:0] LSUHSIZE[1:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/LSUHWDATA[63:0] LSUHWDATA[63:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/LSUHWRITE LSUHWRITE + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/HRDATA[63:0] HRDATA[63:0] HEXRADIX + true + STYLE_DIGITAL @@ -227,13 +310,15 @@ dcache label + - FullPathName + label wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0] CurrState[3:0] - HEXRADIX + BINARYRADIX true STYLE_DIGITAL + dcache fsm @@ -241,28 +326,43 @@ label + FullPathName wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0] HTRANS[1:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HWRITE HWRITE + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HBURST[2:0] HBURST[2:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0] HSIZE[2:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HADDR[31:0] HADDR[31:0] HEXRADIX + true + STYLE_DIGITAL wallypipelinedsoc/core/HRDATA[63:0] @@ -270,22 +370,427 @@ HEXRADIX + FullPathName wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0] HWDATA[63:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HREADY HREADY + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ebu.ebu/HRESP HRESP + true + STYLE_DIGITAL - - wallypipelinedsoc/core/HRDATA[63:0] - HRDATA[63:0] + + uart + label + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/DTRb + DTRb + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/INTR + INTR + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b + OUT1b + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b + OUT2b + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/RTSb + RTSb + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb + RXRDYb + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/SIN + SIN + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/SOUT + SOUT + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb + TXRDYb + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0] + DLL[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0] + DLM[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0] + FCR[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled + fifoenabled + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0] + IER[3:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0] + intrID[2:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0] + LCR[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0] + LSR[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0] + MCR[4:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0] + MSR[3:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0] + RBR[10:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr + rxdataavailintr + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready + rxdataready + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP + RXerrIP + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1 + RXerrIP_1 + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0] + rxfifoentries[3:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered + rxfifotriggered + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr + rxparityerr + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0] + rxstate[1:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0] + SCR[7:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0] + txstate[1:0] + HEXRADIX + true + STYLE_DIGITAL + + + + FullPathName + wallypipelinedsoc/core/hzu/StallM + StallM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/mretM + mretM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/sretM + sretM + true + STYLE_DIGITAL + + + faults + label + + FullPathName + wallypipelinedsoc/core/hzu/BreakpointFaultM + BreakpointFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/hzu/EcallFaultM + EcallFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM + IllegalInstrFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM + InstrAccessFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM + InstrPageFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM + LoadAccessFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM + LoadMisalignedFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM + LoadPageFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM + StoreAmoAccessFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM + StoreAmoMisalignedFaultM + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM + StoreAmoPageFaultM + true + STYLE_DIGITAL + + + + FullPathName + wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0] + csrs.SCAUSE_REGW[63:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0] + MCAUSE_REGW[63:0] + HEXRADIX + true + STYLE_DIGITAL + + + label + wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] + CurrState[3:0] + HEXRADIX + icache fsm + + + label + wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] + CurrState[2:0] + HEXRADIX + ifu bus fsm + + + wallypipelinedsoc/core/ifu/PCNextF[63:0] + PCNextF[63:0] + HEXRADIX + + + wallypipelinedsoc/core/ifu/PCPF[55:0] + PCPF[55:0] + HEXRADIX + + + wallypipelinedsoc/core/lsu/DTLBMissM + DTLBMissM + + + wallypipelinedsoc/core/lsu/DTLBWriteM + DTLBWriteM + + + wallypipelinedsoc/core/lsu/ITLBMissF + ITLBMissF + + + wallypipelinedsoc/core/lsu/ITLBWriteF + ITLBWriteF + + + wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0] + MEPC_REGW[63:0] + HEXRADIX + + + wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0] + SEPC_REGW[63:0] + HEXRADIX + + + wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0] + rf[2]__0[63:0] HEXRADIX diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index c0513ac68..9cd2e82a9 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -154,7 +154,7 @@ module uartPC16550D( //DLL <= #1 8'd38; // 35Mhz //DLL <= #1 8'd11; // 10 Mhz //DLL <= #1 8'd33; // 30 Mhz - DLL <= #1 8'd11; // 30 Mhz 230400 + DLL <= #1 8'd8; // 30 Mhz 230400 DLM <= #1 8'b0; end else begin DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. @@ -178,7 +178,7 @@ module uartPC16550D( // freq /baud / 16 = div //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in - 3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in + 3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing 3'b011: LCR <= #1 Din;