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Fix compile errors from const not actually being constant (why does Verilog do this)

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This commit is contained in:
Jarred Allen 2021-03-24 00:58:56 -04:00
parent 4410944049
commit a51257abca
2 changed files with 19 additions and 11 deletions
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12
wally-pipelined/src/cache/dmapped.sv vendored
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@ -43,13 +43,13 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
output logic DataValid output logic DataValid
); );
integer TAGWIDTH = `XLEN-$clog2(NUMLINES)-$clog2(LINESIZE); localparam integer SETWIDTH = $clog2(NUMLINES);
integer SETWIDTH = $clog2(NUMLINES); localparam integer OFFSETWIDTH = $clog2(LINESIZE/8);
integer OFFSETWIDTH = $clog2(LINESIZE/8); localparam integer TAGWIDTH = `XLEN-SETWIDTH-OFFSETWIDTH;
logic [NUMLINES-1:0][WORDSIZE-1:0] LineOutputs; logic [NUMLINES-1:0][WORDSIZE-1:0] LineOutputs;
logic [NUMLINES-1:0] ValidOutputs; logic [NUMLINES-1:0] ValidOutputs;
logic [NUMLINES-1:0][TAGSIZE-1:0] TagOutputs; logic [NUMLINES-1:0][TAGWIDTH-1:0] TagOutputs;
logic [OFFSETWIDTH-1:0] WordSelect; logic [OFFSETWIDTH-1:0] WordSelect;
logic [`XLEN-1:0] ReadPAdr; logic [`XLEN-1:0] ReadPAdr;
logic [SETWIDTH-1:0] ReadSet, WriteSet; logic [SETWIDTH-1:0] ReadSet, WriteSet;
@ -70,14 +70,14 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
genvar i; genvar i;
generate generate
for (i=0; i < NUMLINES; i++) begin for (i=0; i < NUMLINES; i++) begin
rocacheline #(LINESIZE, TAGSIZE, WORDSIZE) lines[NUMLINES]( rocacheline #(LINESIZE, TAGWIDTH, WORDSIZE) lines (
.*, .*,
.WriteEnable(WriteEnable & (WriteSet == i)), .WriteEnable(WriteEnable & (WriteSet == i)),
.WriteData(WriteLine), .WriteData(WriteLine),
.WriteTag(WriteTag), .WriteTag(WriteTag),
.DataWord(LineOutputs[i]), .DataWord(LineOutputs[i]),
.DataTag(TagOutputs[i]), .DataTag(TagOutputs[i]),
.DataValid(ValidOutputs[i]), .DataValid(ValidOutputs[i])
); );
end end
endgenerate endgenerate

18
wally-pipelined/src/cache/line.sv vendored
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@ -44,17 +44,25 @@ module rocacheline #(parameter LINESIZE = 256, parameter TAGSIZE = 32, parameter
output logic DataValid output logic DataValid
); );
logic [LINESIZE-1:0] DataLine; localparam integer OFFSETSIZE = $clog2(LINESIZE/8);
logic [$clog2(LINESIZE/8)-1:0] AlignedWordSelect; localparam integer NUMWORDS = LINESIZE/WORDSIZE;
logic [NUMWORDS-1:0][WORDSIZE-1:0] DataLinesIn, DataLinesOut;
flopenr #(1) ValidBitFlop(clk, reset, WriteEnable | flush, ~flush, DataValid); flopenr #(1) ValidBitFlop(clk, reset, WriteEnable | flush, ~flush, DataValid);
flopenr #(TAGSIZE) TagFlop(clk, reset, WriteEnable, WriteTag, DataTag); flopenr #(TAGSIZE) TagFlop(clk, reset, WriteEnable, WriteTag, DataTag);
flopenr #(LINESIZE) LineFlop(clk, reset, WriteEnable, WriteData, DataLine);
genvar i;
generate
for (i=0; i < NUMWORDS; i++) begin
assign DataLinesIn[i] = WriteData[NUMWORDS*i+WORDSIZE-1:NUMWORDS*i];
flopenr #(LINESIZE) LineFlop(clk, reset, WriteEnable, DataLinesIn[i], DataLinesOut[i]);
end
endgenerate
always_comb begin always_comb begin
assign AlignedWordSelect = {WordSelect[$clog2(LINESIZE/8)-1:$clog2(WORDSIZE)], {$clog2(WORDSIZE){'b0}}}; assign DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]];
assign DataWord = DataLine[WORDSIZE+AlignedWordSelect-1:AlignedWordSelect];
end end
endmodule endmodule