From a5087818baa0b990fbba648f2f4f33cd938a9c1d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 24 Apr 2023 12:20:33 -0700
Subject: [PATCH] Commented about Sstvecd trap vector alignment

---
 src/privileged/csr.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index db142de5f..9f3ae89b9 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -158,7 +158,7 @@ module csr #(parameter
     assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition
     mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
   end else 
-    assign TrapVectorM = TVecAlignedM;
+    assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd
 
   // Trap Returns
   // A trap sets the PC to TrapVector