From a4ca024025c791a1822c00eb02bc3c2ff1810cd7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 20:03:14 -0800 Subject: [PATCH] Lint progress --- config/buildroot/config.vh | 184 --------------------------------- config/derivlist.txt | 17 ++- config/shared/config-shared.vh | 2 +- sim/lint-wally | 29 ++++-- 4 files changed, 39 insertions(+), 193 deletions(-) delete mode 100644 config/buildroot/config.vh diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh deleted file mode 100644 index 6629af297..000000000 --- a/config/buildroot/config.vh +++ /dev/null @@ -1,184 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 0; - -localparam MISA = (32'h0014112D); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 1; -localparam ZICBOM_SUPPORTED = 1; -localparam ZICBOZ_SUPPORTED = 1; -localparam ZICBOP_SUPPORTED = 1; -localparam ZICCLSM_SUPPORTED = 1; -localparam ZICOND_SUPPORTED = 1; -localparam SVPBMT_SUPPORTED = 1; -localparam SVNAPOT_SUPPORTED = 1; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h00001FFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h00001FFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ; -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b1; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b1; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Bus Interface width -localparam AHBW = 32'd64; - -// AHB -localparam RAM_LATENCY = 32'b0; -localparam BURST_EN = 1; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 0; -localparam SPI_LOOPBACK_TEST = 0; - -// Hardware configuration -localparam UART_PRESCALE = 32'd0; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd53; -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd20; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; -localparam INSTR_CLASS_PRED = 1; - -localparam SVADU_SUPPORTED = 1; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 1; -localparam ZBB_SUPPORTED = 1; -localparam ZBC_SUPPORTED = 1; -localparam ZBS_SUPPORTED = 1; - -// New compressed instructions -localparam ZCB_SUPPORTED = 1; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" diff --git a/config/derivlist.txt b/config/derivlist.txt index 581922b9c..5496dd1db 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -41,8 +41,8 @@ RESET_VECTOR 64'h1000 UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_PRELOAD 1 GPIO_LOOPBACK_TEST 0 -SPI_LOOPBACK_TEST 0 -UART_PRESCALE 0 +SPI_LOOPBACK_TEST 0 +UART_PRESCALE 32'd0 PLIC_NUM_SRC 32'd53 # fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) @@ -119,26 +119,33 @@ MISA (32'h00000104 | 1 << 18 | 1 << 20) deriv div_2_1_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_2_2_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_2_4_rv32gc rv32gc RADIX 32'd2 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_4_1_rv32gc rv32gc RADIX 32'd4 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_4_2_rv32gc rv32gc RADIX 32'd4 +IDIV_ON_FPU 0 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_4_4_rv32gc rv32gc RADIX 32'd4 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc IDIV_ON_FPU 1 @@ -161,26 +168,32 @@ IDIV_ON_FPU 1 deriv div_2_1_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_2_2_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_2_4_rv64gc rv64gc RADIX 32'd2 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_4_1_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd1 +IDIV_ON_FPU 0 deriv div_4_2_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd2 +IDIV_ON_FPU 0 deriv div_4_4_rv64gc rv64gc RADIX 32'd4 DIVCOPIES 32'd4 +IDIV_ON_FPU 0 deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc IDIV_ON_FPU 1 diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index ba215785c..6f25b0cc5 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -103,7 +103,7 @@ localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r intege localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk) localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration -localparam DIVBLEN = $clog2(DIVb); // enough bits to count number of fractional bits +localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit // largest length in IEU/FPU localparam CVTLEN = ((NF 0 ); then + echo -e "${RED}Linting failed for $fails configurations" + exit 1 +fi +echo -e "${GREEN}All lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include config.vh are found