mirror of
https://github.com/openhwgroup/cvw
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fcvt.sv cleanup
This commit is contained in:
Katherine Parry
parent
0cc07fda1b
commit
a4bd128978
@ -1,95 +1,122 @@
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// `include "wally-config.vh"
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`include "wally-config.vh"
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module fcvt (
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input logic [63:0] X,
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input logic [64-1:0] SrcAE,
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input logic [3:0] FOpCtrlE,
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input logic [2:0] FrmE,
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input logic FmtE,
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output logic [63:0] CvtResE,
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output logic [4:0] CvtFlgE);
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input logic [63:0] X, // floating point input
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input logic [`XLEN-1:0] SrcAE, // integer input
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input logic [3:0] FOpCtrlE, // chooses which instruction is done (full list below)
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input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic FmtE, // precision 1 = double 0 = single
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output logic [63:0] CvtResE, // convert final result
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output logic [4:0] CvtFlgE); // convert flags {invalid, divide by zero, overflow, underflow, inexact}
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logic [10:0] XExp;
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logic [51:0] XFrac;
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logic XSgn;
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logic [10:0] ResExp,TmpExp;
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logic [51:0] ResFrac;
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logic ResSgn;
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logic [10:0] NormCnt;
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logic XSgn; // FP input's sign
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logic [10:0] XExp; // FP input's exponent
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logic [51:0] XFrac; // FP input's fraction
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logic ResSgn; // FP result's sign
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logic [10:0] ResExp,TmpExp; // FP result's exponent
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logic [51:0] ResFrac; // FP result's fraction
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logic [5:0] LZResP; // lz output
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// logic LZResV;
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logic [11:0] Bias; // 1023 for double, 127 for single
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logic [7:0] Bits, SubBits;
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logic [64+51:0] ShiftedManTmp;
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logic [64+51:0] ShiftVal;
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logic [64+1:0] ShiftedMan;
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logic [64:0] RoundedTmp;
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logic [63:0] Rounded;
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logic [12:0] ExpVal, ShiftCnt;
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logic [64-1:0] PosInt;
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logic [7:0] Bits; // how many bits are in the integer result
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logic [7:0] SubBits; // subtract these bits from the exponent (FP result)
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logic [`XLEN+51:0] ShiftedManTmp; // Shifted mantissa
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logic [`XLEN+51:0] ShiftVal; // value being shifted (to int - XMan, to FP - |integer input|)
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logic [`XLEN+1:0] ShiftedMan; // shifted mantissa truncated
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logic [64:0] RoundedTmp; // full size rounded result - in case of overfow
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logic [63:0] Rounded; // rounded result
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logic [12:0] ExpVal; // unbiased X exponent
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logic [12:0] ShiftCnt; // how much is the mantissa shifted
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logic [`XLEN-1:0] IntIn; // trimed integer input
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logic [`XLEN-1:0] PosInt; // absolute value of the integer input
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logic [63:0] CvtIntRes; // interger result from the fp -> int instructions
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logic [63:0] CvtFPRes; // floating point result from the int -> fp instructions
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logic XFracZero; // is the fraction of X zero?
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logic Of, Uf; // did the integer result underflow or overflow
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logic XExpZero; // is X's exponent zero
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logic XExpMax; // is the exponent all ones
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logic XNaN, XDenorm, XInf, XZero; // is X a special value
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logic Guard, Round, LSB, Sticky; // bits used to determine rounding
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logic Plus1,CalcPlus1; // do you add one for rounding
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logic SgnRes; // sign of the floating point result
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logic Res64, In64; // is the result or input 64 bits
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logic RoundMSB; // most significant bit of the fraction
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logic RoundSgn; // sign of the rounded result
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logic [64-1:0] CvtIntRes;
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logic [63:0] CvtRes;
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logic XFracZero, Of,Uf;
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logic XExpMax;
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logic XNaN, XDenorm, XInf, XZero;
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logic Plus1,CalcPlus1, Guard, Round, LSB, Sticky;
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logic SgnRes, In64;
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logic Res64;
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logic RoundMSB;
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logic RoundSgn;
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logic XExpZero;
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// fcvt.w.s = 0010 -
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// fcvt.wu.s = 0110 -
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// FOpCtrlE:
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// fcvt.w.s = 0010
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// fcvt.wu.s = 0110
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// fcvt.s.w = 0001
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// fcvt.s.wu = 0101
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// fcvt.l.s = 1010 -
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// fcvt.lu.s = 1110 -
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// fcvt.l.s = 1010
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// fcvt.lu.s = 1110
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// fcvt.s.l = 1001
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// fcvt.s.lu = 1101
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// fcvt.w.d = 0010 -
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// fcvt.wu.d = 0110 -
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// fcvt.w.d = 0010
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// fcvt.wu.d = 0110
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// fcvt.d.w = 0001
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// fcvt.d.wu = 0101
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// fcvt.l.d = 1010 -
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// fcvt.lu.d = 1110 -
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// fcvt.d.l = 1001 --
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// fcvt.d.lu = 1101 --
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// {long, unsigned, to int, from int} Fmt controls the output for fp -> fp
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// fcvt.l.d = 1010
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// fcvt.lu.d = 1110
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// fcvt.d.l = 1001
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// fcvt.d.lu = 1101
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// {long, unsigned, to int, from int}
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// split the input into it's various parts
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assign XSgn = X[63];
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assign XExp = FmtE ? X[62:52] : {3'b0, X[62:55]};
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assign XFrac = FmtE ? X[51:0] : {X[54:32], 29'b0};
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assign XExpZero = ~|XExp;
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// determine if the exponent and fraction are all zero or ones
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assign XExpZero = ~|XExp;
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assign XFracZero = ~|XFrac;
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assign XExpMax = FmtE ? &XExp[10:0] : &XExp[7:0];
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// determine if X is a special value
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assign XNaN = XExpMax & ~XFracZero;
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assign XDenorm = XExpZero & ~XFracZero;
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assign XInf = XExpMax & XFracZero;
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assign XZero = XExpZero & XFracZero;
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// calculate signals based off the input and output's size
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assign Bias = FmtE ? 12'h3ff : 12'h7f;
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assign Res64 = ((FOpCtrlE==4'b1010 || FOpCtrlE==4'b1110) | (FmtE&(FOpCtrlE==4'b0001 | FOpCtrlE==4'b0101 | FOpCtrlE==4'b0000 | FOpCtrlE==4'b1001 | FOpCtrlE==4'b1101)));
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assign In64 = ((FOpCtrlE==4'b1001 || FOpCtrlE==4'b1101) | (FmtE&(FOpCtrlE==4'b0010 | FOpCtrlE==4'b0110 | FOpCtrlE==4'b1010 | FOpCtrlE==4'b1110) | (FOpCtrlE==4'b1101 & ~FmtE)));
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assign SubBits = In64 ? 8'd64 : 8'd32;
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assign Bits = Res64 ? 8'd64 : 8'd32;
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// calulate the unbiased exponent
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assign ExpVal = XExp - Bias + XDenorm;
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////////////////////////////////////////////////////////
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logic [64-1:0] IntIn;
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// position the input in the most significant bits
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assign IntIn = FOpCtrlE[3] ? SrcAE : {SrcAE[31:0], 32'b0};
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// make the integer positive
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assign PosInt = IntIn[64-1]&~FOpCtrlE[2] ? -IntIn : IntIn;
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// determine the integer's sign
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assign ResSgn = ~FOpCtrlE[2] ? IntIn[64-1] : 1'b0;
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// This did not work \/
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// generate
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// if(`XLEN == 64)
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// lz64 lz(LZResP, LZResV, PosInt);
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// else if(`XLEN == 32) begin
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// assign LZResP[5] = 1'b0;
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// lz32 lz(LZResP[4:0], LZResV, PosInt);
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// end
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// endgenerate
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// Leading one detector
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logic [8:0] i;
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always_comb begin
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i = 0;
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while (~PosInt[64-1-i] && i <= 64) i = i+1; // search for leading one
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NormCnt = i+1; // compute shift count
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LZResP = i+1; // compute shift count
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end
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assign TmpExp = i==64 ? 0 : Bias + SubBits - NormCnt;
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// if no one was found set to zero otherwise calculate the exponent
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assign TmpExp = i==64 ? 0 : Bias + SubBits - LZResP;
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@ -97,15 +124,21 @@ module fcvt (
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////////////////////////////////////////////
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// select the shift value and amount based on operation (to fp or int)
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assign ShiftCnt = FOpCtrlE[1] ? ExpVal : LZResP;
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assign ShiftVal = FOpCtrlE[1] ? {{`XLEN-2{1'b0}}, ~(XDenorm|XZero), XFrac} : {PosInt, 52'b0};
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assign ShiftCnt = FOpCtrlE[1] ? ExpVal : NormCnt;
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assign ShiftVal = FOpCtrlE[1] ? {{64-2{1'b0}}, ~(XDenorm|XZero), XFrac} : {PosInt, 52'b0};
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//if shift = -1 then shift one bit right for round to nearest (shift over 2 never rounds)
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// if the shift is negitive add bit for sticky bit
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// if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds)
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// if the shift is negitive add a bit for sticky bit calculation
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// otherwise shift left
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assign ShiftedManTmp = &ShiftCnt ? {{64-1{1'b0}}, ~(XDenorm|XZero), XFrac[51:1]} : ShiftCnt[12] ? {115'b0, ~XZero} : ShiftVal << ShiftCnt;
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assign ShiftedManTmp = &ShiftCnt ? {{`XLEN-1{1'b0}}, ~(XDenorm|XZero), XFrac[51:1]} : ShiftCnt[12] ? {{`XLEN+51{1'b0}}, ~XZero} : ShiftVal << ShiftCnt;
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// truncate the shifted mantissa
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assign ShiftedMan = ShiftedManTmp[64+51:50];
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// calculate sticky bit
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// - take into account the possible right shift from before
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// - the sticky bit calculation covers three diffrent sizes depending on the opperation
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assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XFrac[0] | (FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]);
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@ -126,33 +159,45 @@ module fcvt (
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endcase
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end
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// dont tound if the result is exact
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assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZero&FOpCtrlE[1]);
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// round the shifted mantissa
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assign RoundedTmp = ShiftedMan[64+1:2] + Plus1;
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assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + Plus1 : {{TmpExp, ShiftedMan[64+1:43]} + Plus1, 29'b0} ;
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// fit the rounded result into the appropriate size and take the 2's complement if needed
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assign Rounded = Res64 ? XSgn&FOpCtrlE[1] ? -RoundedTmp[63:0] : RoundedTmp[63:0] :
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XSgn ? {{32{1'b1}}, -RoundedTmp[31:0]} : {32'b0, RoundedTmp[31:0]};
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// extract the MSB and Sign for later use (will be used to determine underflow and overflow)
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assign RoundMSB = Res64 ? RoundedTmp[64] : RoundedTmp[32];
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assign RoundSgn = Res64 ? Rounded[63] : Rounded[31];
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// Choose result
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// double to unsigned long
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// >2^64-1 or +inf or NaN - all 1's
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// <0 or -inf - zero
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// otherwise rounded result
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//assign Of = (~XSgn&($signed(ShiftCnt) >= $signed(Bits))) | (RoundMSB&(ShiftCnt==(Bits-1))) | (~XSgn&XInf) | XNaN;
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// check if the result overflows
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assign Of = (~XSgn&($signed(ShiftCnt) >= $signed(Bits))) | (~XSgn&RoundSgn&~FOpCtrlE[2]) | (RoundMSB&(ShiftCnt==(Bits-1))) | (~XSgn&XInf) | XNaN;
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// check if the result underflows (this calculation changes if the result is signed or unsigned)
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assign Uf = FOpCtrlE[2] ? XSgn&~XZero | (XSgn&XInf) | (XSgn&~XZero&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgn&XInf) | (XSgn&($signed(ShiftCnt) >= $signed(Bits))) | (XSgn&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgn | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded;
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// calculate the result's sign
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assign SgnRes = ~FOpCtrlE[3] & FOpCtrlE[1];
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// select the integer result
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assign CvtIntRes = Of ? FOpCtrlE[2] ? SgnRes ? {32'b0, {32{1'b1}}}: {64{1'b1}} : SgnRes ? {33'b0, {31{1'b1}}}: {1'b0, {63{1'b1}}} :
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Uf ? FOpCtrlE[2] ? 64'b0 : SgnRes ? {32'b0, 1'b1, 31'b0} : {1'b1, 63'b0} :
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Rounded[64-1:0];
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assign CvtRes = FmtE ? {ResSgn, ResExp, ResFrac} : {ResSgn, ResExp[7:0], ResFrac, 3'b0};
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assign CvtResE = FOpCtrlE[0] ? CvtRes : CvtIntRes;
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// select the floating point result
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assign CvtFPRes = FmtE ? {ResSgn, ResExp, ResFrac} : {ResSgn, ResExp[7:0], ResFrac, 3'b0};
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// select the result
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assign CvtResE = FOpCtrlE[0] ? CvtFPRes : CvtIntRes;
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// calculate the flags
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// - to int only sets the invalid flag
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// - from int only sets the inexact flag
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assign CvtFlgE = {(Of | Uf)&FOpCtrlE[1], 3'b0, (Guard|Round|Sticky)&FOpCtrlE[0]};
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@ -40,8 +40,7 @@ module fpu (
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output logic [`XLEN-1:0] FIntResM,
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output logic FDivBusyE, // Is the divison/sqrt unit busy
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic [4:0] SetFflagsM, // FPU flags
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output logic [`XLEN-1:0] FPUResultW); // FPU result
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output logic [4:0] SetFflagsM); // FPU result
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// *** change FMA to do 16 - 32 - 64 - 128 FEXPBITS
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generate
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@ -79,6 +78,9 @@ module fpu (
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logic [63:0] FMAResM, FMAResW;
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logic [4:0] FMAFlgM, FMAFlgW;
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logic [63:0] ReadResW;
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// add/cvt signals
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logic [63:0] FAddResM, FAddResW;
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logic [4:0] FAddFlgM, FAddFlgW;
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@ -102,7 +104,7 @@ module fpu (
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logic [63:0] ClassResE, ClassResM;
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// 64-bit FPU result
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logic [63:0] FPUResult64W;
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logic [63:0] FPUResultW;
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logic [4:0] FPUFlagsW;
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@ -124,7 +126,7 @@ module fpu (
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// regfile instantiation
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fregfile fregfile (clk, reset, FWriteEnW,
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InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
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FPUResult64W,
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FPUResultW,
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FRD1D, FRD2D, FRD3D);
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@ -168,9 +170,9 @@ module fpu (
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.ForwardXE, .ForwardYE, .ForwardZE);
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// forwarding muxs
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mux3 #(64) fxemux(FRD1E, FPUResult64W, FResM, ForwardXE, SrcXE);
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mux3 #(64) fyemux(FRD2E, FPUResult64W, FResM, ForwardYE, SrcYE);
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mux3 #(64) fzemux(FRD3E, FPUResult64W, FResM, ForwardZE, SrcZE);
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mux3 #(64) fxemux(FRD1E, FPUResultW, FResM, ForwardXE, SrcXE);
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mux3 #(64) fyemux(FRD2E, FPUResultW, FResM, ForwardYE, SrcYE);
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mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, ForwardZE, SrcZE);
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// first of two-stage instance of floating-point fused multiply-add unit
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@ -218,8 +220,7 @@ module fpu (
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fcvt fcvt (.X(SrcXE), .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE);
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// output for store instructions
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assign FWriteDataE = FmtE ? SrcYE[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcYE[63:32]};
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//***swap to mux
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mux2 #(`XLEN) FWriteDataMux({{`XLEN-32{1'b0}}, SrcYE[63:32]}, SrcYE[63:64-`XLEN], FmtE, FWriteDataE);
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@ -265,8 +266,7 @@ module fpu (
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mux4 #(64) FResMux(AlignedSrcAM, SgnResM, CmpResM, CvtResM, FResSelM, FResM);
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mux4 #(5) FFlgMux(5'b0, {4'b0, SgnNVM}, {4'b0, CmpNVM}, CvtFlgM, FResSelM, FFlgM);
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//***change to mux
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assign SrcXMAligned = FmtM ? SrcXM[63:64-`XLEN] : {{`XLEN-32{1'b0}}, SrcXM[63:32]};
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mux2 #(`XLEN) SrcXAlignedMux({{`XLEN-32{1'b0}}, SrcXM[63:32]}, SrcXM[63:64-`XLEN], FmtM, SrcXMAligned);
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mux4 #(`XLEN) IntResMux(CmpResM[`XLEN-1:0], SrcXMAligned, ClassResM[`XLEN-1:0], CvtResM[`XLEN-1:0], FIntResSelM, FIntResM);
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@ -318,28 +318,10 @@ module fpu (
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//#########################################
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always_comb begin
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case (FResultSelW)
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3'b000 : FPUResult64W = FmtW ? {ReadDataW, {64-`XLEN{1'b0}}} : {ReadDataW[31:0], 32'b0};
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3'b001 : FPUResult64W = FMAResW;
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3'b010 : FPUResult64W = FAddResW;
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3'b011 : FPUResult64W = FDivResultW;
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3'b100 : FPUResult64W = FResW;
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default : FPUResult64W = 64'bxxxxx;
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endcase
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end
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mux2 #(64) ReadResMux({ReadDataW[31:0], 32'b0}, {ReadDataW, {64-`XLEN{1'b0}}}, FmtW, ReadResW);
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mux5 #(64) FPUResultMux(ReadResW, FMAResW, FAddResW, FDivResultW, FResW, FResultSelW, FPUResultW);
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// interface between XLEN size datapath and double-precision sized
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// floating-point results
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//
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// define offsets for LSB zero extension or truncation
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always_comb begin
|
||||
// zero extension
|
||||
//***turn into mux
|
||||
FPUResultW = FmtW ? FPUResult64W[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FPUResult64W[63:32]};
|
||||
end
|
||||
end else begin // no F_SUPPORTED; tie outputs low
|
||||
assign FStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
@ -350,7 +332,6 @@ module fpu (
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrD = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FPUResultW = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user