From f4e30365933de99111c1357956994f8e36956384 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 7 Sep 2022 16:29:47 -0500 Subject: [PATCH 1/2] Oups fixed order of ending swap with mux between cache and fetch buffer. --- pipelined/src/lsu/lsu.sv | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 4ead5b0f7..01032969f 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -269,7 +269,7 @@ module lsu ( .SelUncachedAdr, .RW(UnCacheRW), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); - mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), + mux2 #(`LLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(LSUHWDATA_noDELAY)); @@ -296,13 +296,13 @@ module lsu ( .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM)); - assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping + assign ReadDataWordMuxM = ReadDataWordM; // from byte swapping assign LSUHBURST = 3'b0; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; end end else begin: nobus // block: bus assign LSUHWDATA = '0; - assign ReadDataWordMuxM = LittleEndianReadDataWordM; + assign ReadDataWordMuxM = ReadDataWordM; assign {BusStall, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; @@ -326,7 +326,10 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// // Subword Accesses ///////////////////////////////////////////////////////////////////////////////////////////// - subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), + // *** Ross Thompson: I think swr needs to be modified to support bigendian. Both the subword + // selected and the sign extension are probably wrong. I think it should be an invertion of + // the address bits and a different bit selected for extension. + subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .LSUPAdrM(LSUPAdrM[2:0]), .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM); @@ -346,10 +349,10 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian bigendianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM)); + bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; - assign LittleEndianReadDataWordM = ReadDataWordM; + assign LittleEndianReadDataWordM = ReadDataWordMuxM; end endmodule From 0904951a8c0a41cfb803aa611f9d2b175dc6e48a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Sep 2022 13:21:37 -0500 Subject: [PATCH 2/2] Oups the ahbinterface.sv was accidentally named abhinterface.sv. --- pipelined/src/ebu/{abhinterface.sv => ahbinterface.sv} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/ebu/{abhinterface.sv => ahbinterface.sv} (100%) diff --git a/pipelined/src/ebu/abhinterface.sv b/pipelined/src/ebu/ahbinterface.sv similarity index 100% rename from pipelined/src/ebu/abhinterface.sv rename to pipelined/src/ebu/ahbinterface.sv