From b911056e669d4e2e714f21bcfcd4ae55379c7d76 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Jan 2023 14:03:44 -0800 Subject: [PATCH 1/2] Changed Wally to CORE-V Wally --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- pipelined/src/cache/subcachelineread.sv | 2 +- pipelined/src/ebu/ahbcacheinterface.sv | 2 +- pipelined/src/ebu/ahbinterface.sv | 2 +- pipelined/src/ebu/amoalu.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 2 +- pipelined/src/ebu/busfsm.sv | 2 +- pipelined/src/ebu/controllerinputstage.sv | 2 +- pipelined/src/ebu/ebu.sv | 2 +- pipelined/src/fpu/fclassify.sv | 2 +- pipelined/src/fpu/fcmp.sv | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- pipelined/src/fpu/fhazard.sv | 2 +- pipelined/src/fpu/fma/fma.sv | 2 +- pipelined/src/fpu/fma/fmaadd.sv | 2 +- pipelined/src/fpu/fma/fmaalign.sv | 2 +- pipelined/src/fpu/fma/fmaexpadd.sv | 2 +- pipelined/src/fpu/fma/fmalza.sv | 2 +- pipelined/src/fpu/fma/fmamult.sv | 2 +- pipelined/src/fpu/fma/fmasign.sv | 2 +- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/fregfile.sv | 2 +- pipelined/src/fpu/fsgninj.sv | 2 +- pipelined/src/fpu/postproc/cvtshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/flags.sv | 2 +- pipelined/src/fpu/postproc/fmashiftcalc.sv | 2 +- pipelined/src/fpu/postproc/negateintres.sv | 2 +- pipelined/src/fpu/postproc/normshift.sv | 2 +- pipelined/src/fpu/postproc/postprocess.sv | 2 +- pipelined/src/fpu/postproc/resultsign.sv | 2 +- pipelined/src/fpu/postproc/round.sv | 2 +- pipelined/src/fpu/postproc/roundsign.sv | 2 +- pipelined/src/fpu/postproc/shiftcorrection.sv | 2 +- pipelined/src/fpu/postproc/specialcase.sv | 2 +- pipelined/src/fpu/unpack.sv | 2 +- pipelined/src/fpu/unpackinput.sv | 2 +- pipelined/src/generic/adder.sv | 2 +- pipelined/src/generic/aplusbeq0.sv | 2 +- pipelined/src/generic/arrs.sv | 2 +- pipelined/src/generic/binencoder.sv | 2 +- pipelined/src/generic/clockgater.sv | 2 +- pipelined/src/generic/counter.sv | 2 +- pipelined/src/generic/csa.sv | 2 +- pipelined/src/generic/decoder.sv | 2 +- pipelined/src/generic/flop/flop.sv | 2 +- pipelined/src/generic/flop/flopen.sv | 2 +- pipelined/src/generic/flop/flopenl.sv | 2 +- pipelined/src/generic/flop/flopenr.sv | 2 +- pipelined/src/generic/flop/flopenrc.sv | 2 +- pipelined/src/generic/flop/flopens.sv | 2 +- pipelined/src/generic/flop/flopr.sv | 2 +- pipelined/src/generic/flop/floprc.sv | 2 +- pipelined/src/generic/flop/synchronizer.sv | 2 +- pipelined/src/generic/lzc.sv | 2 +- pipelined/src/generic/mem/ram1p1rwbe.sv | 2 +- pipelined/src/generic/mem/ram2p1r1wb.sv | 2 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 2 +- pipelined/src/generic/mux.sv | 2 +- pipelined/src/generic/neg.sv | 2 +- pipelined/src/generic/onehotdecoder.sv | 2 +- pipelined/src/generic/or_rows.sv | 2 +- pipelined/src/generic/priorityonehot.sv | 2 +- pipelined/src/generic/prioritythermometer.sv | 2 +- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ieu/alu.sv | 2 +- pipelined/src/ieu/comparator.sv | 2 +- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/extend.sv | 2 +- pipelined/src/ieu/forward.sv | 2 +- pipelined/src/ieu/ieu.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/ieu/shifter.sv | 2 +- pipelined/src/ifu/BTBPredictor.sv | 2 +- pipelined/src/ifu/RAsPredictor.sv | 2 +- pipelined/src/ifu/bpred.sv | 2 +- pipelined/src/ifu/decompress.sv | 2 +- pipelined/src/ifu/foldedgshare.sv | 2 +- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/globalhistory.sv | 2 +- pipelined/src/ifu/gshare.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/ifu/irom.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor2.sv | 2 +- pipelined/src/ifu/satCounter2.sv | 2 +- pipelined/src/ifu/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/speculativegshare.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/atomic.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/lsu/endianswap.sv | 2 +- pipelined/src/lsu/lrsc.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/lsu/subwordread.sv | 2 +- pipelined/src/lsu/subwordwrite.sv | 2 +- pipelined/src/lsu/swbytemask.sv | 2 +- pipelined/src/mdu/intdivrestoring.sv | 2 +- pipelined/src/mdu/intdivrestoringstep.sv | 2 +- pipelined/src/mdu/mdu.sv | 2 +- pipelined/src/mdu/mul.sv | 2 +- pipelined/src/mmu/adrdec.sv | 2 +- pipelined/src/mmu/adrdecs.sv | 2 +- pipelined/src/mmu/hptw.sv | 2 +- pipelined/src/mmu/mmu.sv | 2 +- pipelined/src/mmu/pmachecker.sv | 2 +- pipelined/src/mmu/pmpadrdec.sv | 2 +- pipelined/src/mmu/pmpchecker.sv | 2 +- pipelined/src/mmu/tlb.sv | 2 +- pipelined/src/mmu/tlbcam.sv | 2 +- pipelined/src/mmu/tlbcamline.sv | 2 +- pipelined/src/mmu/tlbcontrol.sv | 2 +- pipelined/src/mmu/tlblru.sv | 2 +- pipelined/src/mmu/tlbmixer.sv | 2 +- pipelined/src/mmu/tlbram.sv | 2 +- pipelined/src/mmu/tlbramline.sv | 2 +- pipelined/src/mmu/vm64check.sv | 2 +- pipelined/src/privileged/csr.sv | 2 +- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 2 +- pipelined/src/privileged/csrm.sv | 2 +- pipelined/src/privileged/csrs.sv | 2 +- pipelined/src/privileged/csrsr.sv | 2 +- pipelined/src/privileged/csru.sv | 2 +- pipelined/src/privileged/privdec.sv | 2 +- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 2 +- pipelined/src/privileged/privpiperegs.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- pipelined/src/uncore/ahbapbbridge.sv | 2 +- pipelined/src/uncore/clint_apb.sv | 2 +- pipelined/src/uncore/gpio_apb.sv | 2 +- pipelined/src/uncore/plic_apb.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- pipelined/src/uncore/rom_ahb.sv | 2 +- pipelined/src/uncore/sdc/SDC.sv | 2 +- pipelined/src/uncore/sdc/SDCcounter.sv | 2 +- pipelined/src/uncore/sdc/clkdivider.sv | 2 +- pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/crc7_pipo.sv | 2 +- pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/piso_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv | 2 +- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_dat_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_top.sv | 2 +- pipelined/src/uncore/sdc/simple_timer.sv | 2 +- pipelined/src/uncore/sdc/sipo_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/up_down_counter.sv | 2 +- pipelined/src/uncore/uartPC16550D.sv | 2 +- pipelined/src/uncore/uart_apb.sv | 2 +- pipelined/src/uncore/uncore.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/src/wally/wallypipelinedsocwrapper.v | 2 +- 179 files changed, 179 insertions(+), 179 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index f62de4fe5..23a90db26 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -6,7 +6,7 @@ // // Purpose: Storage for data and meta data. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 7485a5d8c..36005e4e3 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -6,7 +6,7 @@ // Tested for Powers of 2. // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 48b2aec85..657f1f97f 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 202214412..4d25b8d3d 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -6,7 +6,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 2e7c1e96d..6a317e134 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 1bb8bb6a9..6263f4972 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index adb6ef382..98134afee 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/amoalu.sv b/pipelined/src/ebu/amoalu.sv index a771a8cd4..5e1dd8505 100644 --- a/pipelined/src/ebu/amoalu.sv +++ b/pipelined/src/ebu/amoalu.sv @@ -6,7 +6,7 @@ // // Purpose: Performs AMO operations // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 447da7b88..38b0b8ffa 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 5f47fa57b..41be2d2d0 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/controllerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv index 2cd474f05..d84add27e 100644 --- a/pipelined/src/ebu/controllerinputstage.sv +++ b/pipelined/src/ebu/controllerinputstage.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index b0f680b3b..333da0dd8 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index 3e0cf82a1..c2dfa9883 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 2c2b5d343..09881ff0f 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -7,7 +7,7 @@ // // Purpose: Floating-point comparison unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 66602d04f..1363d18e5 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index b6b4af5c0..a47031a76 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 9ff120d45..e5f58b6b6 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index d0580984e..c4cd39183 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 16687442d..863a76037 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 02a84bf1b..4649e9a5b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 7687ce145..a21754516 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 84b3bfbac..4a1d7d133 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 40ae2460f..2fa3fb988 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index d9a72205b..fce047158 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index e82732f78..ef725d977 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index c9d8ff40e..4751db294 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Quotient Digit Selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 73abf3587..c4e341d00 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index bb2ef154a..a7f3f214c 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index bb35e4fd8..04b36c446 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index a9791f733..01b30eb0e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index db1f55223..281f74601 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 156acea80..711502555 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index e290fb400..cd899ebda 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv index fe412b198..a043df7d4 100644 --- a/pipelined/src/fpu/fma/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -7,7 +7,7 @@ // // Purpose: FMA alginment shift // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv index 81db8c81a..dfb31dc4b 100644 --- a/pipelined/src/fpu/fma/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv index 51a992b0f..b9065f056 100644 --- a/pipelined/src/fpu/fma/fmalza.sv +++ b/pipelined/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv index 6bb480d6f..5f30c1666 100644 --- a/pipelined/src/fpu/fma/fmamult.sv +++ b/pipelined/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv index 7f86ee2ca..2664d6c54 100644 --- a/pipelined/src/fpu/fma/fmasign.sv +++ b/pipelined/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 487ce46ab..d9c82e9b5 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index bf6ce6712..393d25b14 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index e66ece117..4c2f14469 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv index eff29e101..8b6dc0263 100644 --- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv +++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index cab267f5f..e2601211c 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv index 92299853a..d8cd47b71 100644 --- a/pipelined/src/fpu/postproc/flags.sv +++ b/pipelined/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 1e7034314..3335b40f7 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv index faeba4b92..8f9cc96dd 100644 --- a/pipelined/src/fpu/postproc/negateintres.sv +++ b/pipelined/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv index 1740ad21f..95024c777 100644 --- a/pipelined/src/fpu/postproc/normshift.sv +++ b/pipelined/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index 9be14644f..c4dcf9f3f 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv index f85a1a0f7..484d21326 100644 --- a/pipelined/src/fpu/postproc/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv index 0cba58ebf..b14d39be0 100644 --- a/pipelined/src/fpu/postproc/round.sv +++ b/pipelined/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv index 1fb497b20..0d376e7dd 100644 --- a/pipelined/src/fpu/postproc/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation ofr rounding // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv index 23fa66b85..0f1e6bd1b 100644 --- a/pipelined/src/fpu/postproc/shiftcorrection.sv +++ b/pipelined/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv index 976b2e57c..6e9e2156e 100644 --- a/pipelined/src/fpu/postproc/specialcase.sv +++ b/pipelined/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 59023ef59..20fb8ed25 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 179e5d543..14a414753 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/adder.sv b/pipelined/src/generic/adder.sv index 58bab0261..b5439a426 100644 --- a/pipelined/src/generic/adder.sv +++ b/pipelined/src/generic/adder.sv @@ -6,7 +6,7 @@ // // Purpose: Adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/aplusbeq0.sv b/pipelined/src/generic/aplusbeq0.sv index afda700db..8dea1143f 100644 --- a/pipelined/src/generic/aplusbeq0.sv +++ b/pipelined/src/generic/aplusbeq0.sv @@ -6,7 +6,7 @@ // // Purpose: Determine if A+B = 0. Used in FP divider. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/arrs.sv b/pipelined/src/generic/arrs.sv index 9d234985f..3930314b5 100644 --- a/pipelined/src/generic/arrs.sv +++ b/pipelined/src/generic/arrs.sv @@ -9,7 +9,7 @@ // arrs takes in the asynchronous reset and outputs an asynchronous // rising edge, but then syncs the falling edge to the posedge clk. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/binencoder.sv b/pipelined/src/generic/binencoder.sv index 7947ebdcf..f62d2aee4 100644 --- a/pipelined/src/generic/binencoder.sv +++ b/pipelined/src/generic/binencoder.sv @@ -5,7 +5,7 @@ // // Purpose: one-hot to binary encoding. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/clockgater.sv b/pipelined/src/generic/clockgater.sv index 4657354e9..b3c2c689a 100644 --- a/pipelined/src/generic/clockgater.sv +++ b/pipelined/src/generic/clockgater.sv @@ -6,7 +6,7 @@ // // Purpose: Clock gater model. Must use standard cell for synthesis. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/counter.sv b/pipelined/src/generic/counter.sv index c530654dc..18e27884f 100644 --- a/pipelined/src/generic/counter.sv +++ b/pipelined/src/generic/counter.sv @@ -6,7 +6,7 @@ // // Purpose: Counter with reset and enable // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/csa.sv b/pipelined/src/generic/csa.sv index 1c540de60..cffef4321 100644 --- a/pipelined/src/generic/csa.sv +++ b/pipelined/src/generic/csa.sv @@ -6,7 +6,7 @@ // // Purpose: 3:2 carry-save adder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv index 7fa4f8eda..de1df16d2 100644 --- a/pipelined/src/generic/decoder.sv +++ b/pipelined/src/generic/decoder.sv @@ -6,7 +6,7 @@ // // Purpose: Binary encoding to one-hot decoder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv index 35afda76d..979c81b11 100644 --- a/pipelined/src/generic/flop/flop.sv +++ b/pipelined/src/generic/flop/flop.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv index ea652aa00..8f447b91f 100644 --- a/pipelined/src/generic/flop/flopen.sv +++ b/pipelined/src/generic/flop/flopen.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv index 4520089a4..db79567a3 100644 --- a/pipelined/src/generic/flop/flopenl.sv +++ b/pipelined/src/generic/flop/flopenl.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv index c0cac076c..bd733aece 100644 --- a/pipelined/src/generic/flop/flopenr.sv +++ b/pipelined/src/generic/flop/flopenr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv index 4003c1ba5..197c55915 100644 --- a/pipelined/src/generic/flop/flopenrc.sv +++ b/pipelined/src/generic/flop/flopenrc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopens.sv b/pipelined/src/generic/flop/flopens.sv index 2b17e01eb..872d34900 100644 --- a/pipelined/src/generic/flop/flopens.sv +++ b/pipelined/src/generic/flop/flopens.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv index 05f03bc85..1fe42277b 100644 --- a/pipelined/src/generic/flop/flopr.sv +++ b/pipelined/src/generic/flop/flopr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/floprc.sv b/pipelined/src/generic/flop/floprc.sv index 76b73ca16..6d084d6c4 100644 --- a/pipelined/src/generic/flop/floprc.sv +++ b/pipelined/src/generic/flop/floprc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv index 6750ffbe1..6e208e95b 100644 --- a/pipelined/src/generic/flop/synchronizer.sv +++ b/pipelined/src/generic/flop/synchronizer.sv @@ -6,7 +6,7 @@ // // Purpose: Two-stage flip-flop synchronizer // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index fb8fbd1c7..5a58cf42c 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -5,7 +5,7 @@ // // Purpose: Leading Zero Counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index d203c500b..374a9a0b2 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index 504a7ea22..ee66e333b 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -16,7 +16,7 @@ // example // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index 36f871763..cc23b252d 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 3c076e0ca..6f6533a6c 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -5,7 +5,7 @@ // // Purpose: Single-ported ROM // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mux.sv b/pipelined/src/generic/mux.sv index a63ae17fe..d4f926673 100644 --- a/pipelined/src/generic/mux.sv +++ b/pipelined/src/generic/mux.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/neg.sv b/pipelined/src/generic/neg.sv index 82d9db339..f7947ce66 100644 --- a/pipelined/src/generic/neg.sv +++ b/pipelined/src/generic/neg.sv @@ -6,7 +6,7 @@ // // Purpose: 2's complement negator // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/onehotdecoder.sv b/pipelined/src/generic/onehotdecoder.sv index eb3408578..f10519691 100644 --- a/pipelined/src/generic/onehotdecoder.sv +++ b/pipelined/src/generic/onehotdecoder.sv @@ -6,7 +6,7 @@ // // Purpose: Bin to one hot decoder. Power of 2 only. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/or_rows.sv b/pipelined/src/generic/or_rows.sv index 77d47b5e3..7f892f764 100644 --- a/pipelined/src/generic/or_rows.sv +++ b/pipelined/src/generic/or_rows.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv index e2c79cd6e..1aa28c889 100644 --- a/pipelined/src/generic/priorityonehot.sv +++ b/pipelined/src/generic/priorityonehot.sv @@ -16,7 +16,7 @@ // in 01011101010100000 // out 00000000000100000 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv index 78f00d88e..0e2ba7dcc 100644 --- a/pipelined/src/generic/prioritythermometer.sv +++ b/pipelined/src/generic/prioritythermometer.sv @@ -12,7 +12,7 @@ // in 01011101010100000 // out 00000000000011111 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index f00837aba..d99cf3941 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 0e2f5118c..041712a7d 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index 103ca187a..579f2c9c6 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -6,7 +6,7 @@ // // Purpose: Branch comparison // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 6fde524fd..d6a204b0d 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -6,7 +6,7 @@ // // Purpose: Top level controller module // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 346fab14b..159d07f6e 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -6,7 +6,7 @@ // // Purpose: Wally Integer Datapath // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index c9ec903a1..feb7f9fbd 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -6,7 +6,7 @@ // // Purpose: // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index b2581cc6b..11fb44181 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -6,7 +6,7 @@ // // Purpose: Determine datapath forwarding // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 20fbe3a9d..9f4a773d6 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 8a937730e..8ac09a911 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3-port register file // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 70e0bb6d5..21573c6c7 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index b8517b630..592d0f6fd 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -9,7 +9,7 @@ // Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want // to encode to reduce storage), valid, target PC. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv index b75a8e20e..b7fbbc5a5 100644 --- a/pipelined/src/ifu/RAsPredictor.sv +++ b/pipelined/src/ifu/RAsPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 322321f1f..29c3556f3 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -9,7 +9,7 @@ // Purpose: Branch prediction unit // Produces a branch prediction based on branch history. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/decompress.sv b/pipelined/src/ifu/decompress.sv index d9d738567..044095f8e 100644 --- a/pipelined/src/ifu/decompress.sv +++ b/pipelined/src/ifu/decompress.sv @@ -6,7 +6,7 @@ // // Purpose: Expand 16-bit compressed instructions to 32 bits // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/foldedgshare.sv index b6d573589..2665f318c 100644 --- a/pipelined/src/ifu/foldedgshare.sv +++ b/pipelined/src/ifu/foldedgshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index 34b5115aa..cf97039c9 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/globalhistory.sv index 0d9156a58..d4f234ac6 100644 --- a/pipelined/src/ifu/globalhistory.sv +++ b/pipelined/src/ifu/globalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/gshare.sv index 9fc7b0823..2fbac5c57 100644 --- a/pipelined/src/ifu/gshare.sv +++ b/pipelined/src/ifu/gshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2e14a83a1..d88ccdf54 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -7,7 +7,7 @@ // Purpose: Instrunction Fetch Unit // PC, branch prediction, instruction cache // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index c547b0a62..ef9284317 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple instruction ROM -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 259596115..7e61d8c3f 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/oldgsharepredictor.sv index d3115c416..627d2c336 100644 --- a/pipelined/src/ifu/oldgsharepredictor.sv +++ b/pipelined/src/ifu/oldgsharepredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/oldgsharepredictor2.sv index a652b6501..047e9e6b9 100644 --- a/pipelined/src/ifu/oldgsharepredictor2.sv +++ b/pipelined/src/ifu/oldgsharepredictor2.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/satCounter2.sv index 7873cb14a..1a0d5a276 100644 --- a/pipelined/src/ifu/satCounter2.sv +++ b/pipelined/src/ifu/satCounter2.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit starting counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv index d367caaf9..7a099e74e 100644 --- a/pipelined/src/ifu/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/speculativeglobalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv index 1ae611aaa..0febd925e 100644 --- a/pipelined/src/ifu/speculativegshare.sv +++ b/pipelined/src/ifu/speculativegshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 336914988..7835fc00c 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -8,7 +8,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 9ba988294..a7d2669a3 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index b2a678ae1..c61acd991 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -6,7 +6,7 @@ // // Purpose: atomic data path. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 716c70215..6e4689ef5 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple memory with bus or cache. -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv index 0e8fe9833..1b3497fa8 100644 --- a/pipelined/src/lsu/endianswap.sv +++ b/pipelined/src/lsu/endianswap.sv @@ -6,7 +6,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index bcf6ae0e2..f4a4b9ffe 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -7,7 +7,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 3117d8577..daf203f8e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -8,7 +8,7 @@ // Top level of the memory-stage core logic // Contains data cache, DTLB, subword read/write datapath, interface to external bus // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index de86b8554..2b8854e5e 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -6,7 +6,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 774e6a500..576079555 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -6,7 +6,7 @@ // // Purpose: Masking and muxing for subword writes // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv index d04a58556..433a5c91f 100644 --- a/pipelined/src/lsu/swbytemask.sv +++ b/pipelined/src/lsu/swbytemask.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoring.sv b/pipelined/src/mdu/intdivrestoring.sv index 5d0b893ac..59ecbe7d6 100644 --- a/pipelined/src/mdu/intdivrestoring.sv +++ b/pipelined/src/mdu/intdivrestoring.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/pipelined/src/mdu/intdivrestoringstep.sv index f9a025d4b..b37afd543 100644 --- a/pipelined/src/mdu/intdivrestoringstep.sv +++ b/pipelined/src/mdu/intdivrestoringstep.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mdu.sv b/pipelined/src/mdu/mdu.sv index 6dcb4791e..0490642c6 100644 --- a/pipelined/src/mdu/mdu.sv +++ b/pipelined/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mul.sv b/pipelined/src/mdu/mul.sv index d53ac074c..a8c4e2966 100644 --- a/pipelined/src/mdu/mul.sv +++ b/pipelined/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Multiply instructions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdec.sv b/pipelined/src/mmu/adrdec.sv index c587ab079..6c0303cca 100644 --- a/pipelined/src/mmu/adrdec.sv +++ b/pipelined/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 40d55a95f..8dc9c45cc 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 8146ccaf2..67e4a83ba 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -11,7 +11,7 @@ // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index a31c97f63..1949bf133 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index 871ceb729..f74cff2a1 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv index 4b1e7d3d2..fb3e2c614 100644 --- a/pipelined/src/mmu/pmpadrdec.sv +++ b/pipelined/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv index 12a8c751f..c6f357a69 100644 --- a/pipelined/src/mmu/pmpchecker.sv +++ b/pipelined/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlb.sv b/pipelined/src/mmu/tlb.sv index 1ca576523..7d5e51bbe 100644 --- a/pipelined/src/mmu/tlb.sv +++ b/pipelined/src/mmu/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv index 2bcce3932..79a1f21e9 100644 --- a/pipelined/src/mmu/tlbcam.sv +++ b/pipelined/src/mmu/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcamline.sv b/pipelined/src/mmu/tlbcamline.sv index 84bafc9fa..627f496dc 100644 --- a/pipelined/src/mmu/tlbcamline.sv +++ b/pipelined/src/mmu/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index baf41e962..eb0735130 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index ca5530339..ee5ac7fe6 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbmixer.sv b/pipelined/src/mmu/tlbmixer.sv index efeb19d99..71e5ca917 100644 --- a/pipelined/src/mmu/tlbmixer.sv +++ b/pipelined/src/mmu/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbram.sv b/pipelined/src/mmu/tlbram.sv index 4712d46d4..8b2c59d68 100644 --- a/pipelined/src/mmu/tlbram.sv +++ b/pipelined/src/mmu/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbramline.sv b/pipelined/src/mmu/tlbramline.sv index 42d8bf318..6c3a30790 100644 --- a/pipelined/src/mmu/tlbramline.sv +++ b/pipelined/src/mmu/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/vm64check.sv b/pipelined/src/mmu/vm64check.sv index 550937ac3..ad4ff4cea 100644 --- a/pipelined/src/mmu/vm64check.sv +++ b/pipelined/src/mmu/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 82d500a78..003e5bf47 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 191aafd86..427c8152f 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -9,7 +9,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index c363bb0df..9d0c6aff5 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index f93e8fcf3..1d621da9d 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -8,7 +8,7 @@ // Purpose: Machine-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 2e0e4d5bd..d9590d0f8 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 1550ef435..705052975 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 56df95032..0bf35694b 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -8,7 +8,7 @@ // See RISC-V Privileged Mode Specification 20190608 Table 2.2 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 9febaa3dd..d2729e9f1 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index c8b7a21ba..edaca1da4 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index c962dc2f9..1eb6b4dbb 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -7,7 +7,7 @@ // Purpose: Track privilege mode // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv index f0d4ea897..52761855c 100644 --- a/pipelined/src/privileged/privpiperegs.sv +++ b/pipelined/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index d2d38fc2e..05f1f6e97 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -7,7 +7,7 @@ // Purpose: Handle Traps: Exceptions and Interrupts // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv index 93d51ade7..2a3656955 100644 --- a/pipelined/src/uncore/ahbapbbridge.sv +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index b3a9802bd..e80be7d7c 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv index 22032fae7..f84707a84 100644 --- a/pipelined/src/uncore/gpio_apb.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -8,7 +8,7 @@ // See FE310-G002-Manual-v19p05 for specifications // No interrupts, drive strength, or pull-ups supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index 519fe4a01..bf5803346 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -13,7 +13,7 @@ // Do we detect requests as level-triggered or edge-trigged? // If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests? // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index e3b72bd04..2a0a1b3ff 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core, with AHB interface // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv index f68cffdc2..9aba4d68d 100644 --- a/pipelined/src/uncore/rom_ahb.sv +++ b/pipelined/src/uncore/rom_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip ROM, external to core // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index 06320c52a..f756e45e1 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -6,7 +6,7 @@ // // Purpose: SDC interface to AHBLite BUS. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv index 39d75a2ff..8009790f2 100644 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ b/pipelined/src/uncore/sdc/SDCcounter.sv @@ -7,7 +7,7 @@ // // Purpose: basic up counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv index 7875bf4e8..44f582571 100644 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ b/pipelined/src/uncore/sdc/clkdivider.sv @@ -7,7 +7,7 @@ // // Purpose: clock divider for sd flash // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv index 257ee37cf..4cc43211a 100644 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv @@ -8,7 +8,7 @@ // Purpose: CRC16 generator SIPO using register_ce // w/o appending any zero-bits to the message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv index 201b1ec24..797e62f64 100644 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ b/pipelined/src/uncore/sdc/crc7_pipo.sv @@ -9,7 +9,7 @@ // clock cycle! // w/o appending any zero-bits to the message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv index ed3e5464e..8f7fb928e 100644 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv @@ -7,7 +7,7 @@ // Purpose: CRC7 generator SIPO using register_ce // w/o appending any zero-bits othe message // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv index 96f82a622..2d332b435 100644 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv @@ -5,7 +5,7 @@ // Modified: Ross Thompson September 18, 2021 // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv index 80f3b95ab..1956cbc7a 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv index 71e77cbc9..d08179728 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv index a6fae4c52..327a833cd 100644 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv @@ -15,7 +15,7 @@ // It must be synchronized with 50 MHz and held for a minimum period of a full // 400 KHz pulse width. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv index 38c2494cc..b1b4a163d 100644 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv @@ -6,7 +6,7 @@ // // Purpose: Finite state machine for the SD CMD bus // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv index 3f2d99f12..49ba94bf1 100644 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv @@ -8,7 +8,7 @@ // bus of the SD card. // 14 State Mealy FSM + Safe state = 15 State Mealy FSM // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv index cdc62d8ef..7a9c35fa6 100644 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ b/pipelined/src/uncore/sdc/sd_top.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv index 9bbd32c2a..0e6afa75c 100644 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ b/pipelined/src/uncore/sdc/simple_timer.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv index c3d526863..ed55559dc 100644 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv @@ -9,7 +9,7 @@ // bit first. // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv index f0c47a2fe..894df3696 100644 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ b/pipelined/src/uncore/sdc/up_down_counter.sv @@ -6,7 +6,7 @@ // // Purpose: basic up counter // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 211f7507a..f627aca89 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not ye implemented*** // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index 2f562dad8..f1d6fd7a6 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model *** // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 372b2dbf7..1ca9d3cb4 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index b48dcd28c..b6d04b62c 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 8f057854c..69c3ce04e 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index faf762285..a812924c6 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the Wally configurable RISC-V project. +// A component of the CORE-V Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // From 7d93659f6b4af2753130a7b05dcec253659d5e20 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Jan 2023 15:15:08 -0800 Subject: [PATCH 2/2] changed name to CORE-V-WALLY --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- pipelined/src/cache/subcachelineread.sv | 2 +- pipelined/src/ebu/ahbcacheinterface.sv | 2 +- pipelined/src/ebu/ahbinterface.sv | 2 +- pipelined/src/ebu/amoalu.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 2 +- pipelined/src/ebu/busfsm.sv | 2 +- pipelined/src/ebu/controllerinputstage.sv | 2 +- pipelined/src/ebu/ebu.sv | 2 +- pipelined/src/fpu/fclassify.sv | 2 +- pipelined/src/fpu/fcmp.sv | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- pipelined/src/fpu/fhazard.sv | 2 +- pipelined/src/fpu/fma/fma.sv | 2 +- pipelined/src/fpu/fma/fmaadd.sv | 2 +- pipelined/src/fpu/fma/fmaalign.sv | 2 +- pipelined/src/fpu/fma/fmaexpadd.sv | 2 +- pipelined/src/fpu/fma/fmalza.sv | 2 +- pipelined/src/fpu/fma/fmamult.sv | 2 +- pipelined/src/fpu/fma/fmasign.sv | 2 +- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/fregfile.sv | 2 +- pipelined/src/fpu/fsgninj.sv | 2 +- pipelined/src/fpu/postproc/cvtshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/flags.sv | 2 +- pipelined/src/fpu/postproc/fmashiftcalc.sv | 2 +- pipelined/src/fpu/postproc/negateintres.sv | 2 +- pipelined/src/fpu/postproc/normshift.sv | 2 +- pipelined/src/fpu/postproc/postprocess.sv | 2 +- pipelined/src/fpu/postproc/resultsign.sv | 2 +- pipelined/src/fpu/postproc/round.sv | 2 +- pipelined/src/fpu/postproc/roundsign.sv | 2 +- pipelined/src/fpu/postproc/shiftcorrection.sv | 2 +- pipelined/src/fpu/postproc/specialcase.sv | 2 +- pipelined/src/fpu/unpack.sv | 2 +- pipelined/src/fpu/unpackinput.sv | 2 +- pipelined/src/generic/adder.sv | 2 +- pipelined/src/generic/aplusbeq0.sv | 2 +- pipelined/src/generic/arrs.sv | 2 +- pipelined/src/generic/binencoder.sv | 2 +- pipelined/src/generic/clockgater.sv | 2 +- pipelined/src/generic/counter.sv | 2 +- pipelined/src/generic/csa.sv | 2 +- pipelined/src/generic/decoder.sv | 2 +- pipelined/src/generic/flop/flop.sv | 2 +- pipelined/src/generic/flop/flopen.sv | 2 +- pipelined/src/generic/flop/flopenl.sv | 2 +- pipelined/src/generic/flop/flopenr.sv | 2 +- pipelined/src/generic/flop/flopenrc.sv | 2 +- pipelined/src/generic/flop/flopens.sv | 2 +- pipelined/src/generic/flop/flopr.sv | 2 +- pipelined/src/generic/flop/floprc.sv | 2 +- pipelined/src/generic/flop/synchronizer.sv | 2 +- pipelined/src/generic/lzc.sv | 2 +- pipelined/src/generic/mem/ram1p1rwbe.sv | 2 +- pipelined/src/generic/mem/ram2p1r1wb.sv | 2 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 2 +- pipelined/src/generic/mux.sv | 2 +- pipelined/src/generic/neg.sv | 2 +- pipelined/src/generic/onehotdecoder.sv | 2 +- pipelined/src/generic/or_rows.sv | 2 +- pipelined/src/generic/priorityonehot.sv | 2 +- pipelined/src/generic/prioritythermometer.sv | 2 +- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ieu/alu.sv | 2 +- pipelined/src/ieu/comparator.sv | 2 +- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/extend.sv | 2 +- pipelined/src/ieu/forward.sv | 2 +- pipelined/src/ieu/ieu.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/ieu/shifter.sv | 2 +- pipelined/src/ifu/BTBPredictor.sv | 2 +- pipelined/src/ifu/RAsPredictor.sv | 2 +- pipelined/src/ifu/bpred.sv | 2 +- pipelined/src/ifu/decompress.sv | 2 +- pipelined/src/ifu/foldedgshare.sv | 2 +- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/globalhistory.sv | 2 +- pipelined/src/ifu/gshare.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/ifu/irom.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor2.sv | 2 +- pipelined/src/ifu/satCounter2.sv | 2 +- pipelined/src/ifu/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/speculativegshare.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/atomic.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/lsu/endianswap.sv | 2 +- pipelined/src/lsu/lrsc.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/lsu/subwordread.sv | 2 +- pipelined/src/lsu/subwordwrite.sv | 2 +- pipelined/src/lsu/swbytemask.sv | 2 +- pipelined/src/mdu/intdivrestoring.sv | 2 +- pipelined/src/mdu/intdivrestoringstep.sv | 2 +- pipelined/src/mdu/mdu.sv | 2 +- pipelined/src/mdu/mul.sv | 2 +- pipelined/src/mmu/adrdec.sv | 2 +- pipelined/src/mmu/adrdecs.sv | 2 +- pipelined/src/mmu/hptw.sv | 2 +- pipelined/src/mmu/mmu.sv | 2 +- pipelined/src/mmu/pmachecker.sv | 2 +- pipelined/src/mmu/pmpadrdec.sv | 2 +- pipelined/src/mmu/pmpchecker.sv | 2 +- pipelined/src/mmu/tlb.sv | 2 +- pipelined/src/mmu/tlbcam.sv | 2 +- pipelined/src/mmu/tlbcamline.sv | 2 +- pipelined/src/mmu/tlbcontrol.sv | 2 +- pipelined/src/mmu/tlblru.sv | 2 +- pipelined/src/mmu/tlbmixer.sv | 2 +- pipelined/src/mmu/tlbram.sv | 2 +- pipelined/src/mmu/tlbramline.sv | 2 +- pipelined/src/mmu/vm64check.sv | 2 +- pipelined/src/privileged/csr.sv | 2 +- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 2 +- pipelined/src/privileged/csrm.sv | 2 +- pipelined/src/privileged/csrs.sv | 2 +- pipelined/src/privileged/csrsr.sv | 2 +- pipelined/src/privileged/csru.sv | 2 +- pipelined/src/privileged/privdec.sv | 2 +- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 2 +- pipelined/src/privileged/privpiperegs.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- pipelined/src/uncore/ahbapbbridge.sv | 2 +- pipelined/src/uncore/clint_apb.sv | 2 +- pipelined/src/uncore/gpio_apb.sv | 2 +- pipelined/src/uncore/plic_apb.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- pipelined/src/uncore/rom_ahb.sv | 2 +- pipelined/src/uncore/sdc/SDC.sv | 2 +- pipelined/src/uncore/sdc/SDCcounter.sv | 2 +- pipelined/src/uncore/sdc/clkdivider.sv | 2 +- pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/crc7_pipo.sv | 2 +- pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/piso_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv | 2 +- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_dat_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_top.sv | 2 +- pipelined/src/uncore/sdc/simple_timer.sv | 2 +- pipelined/src/uncore/sdc/sipo_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/up_down_counter.sv | 2 +- pipelined/src/uncore/uartPC16550D.sv | 2 +- pipelined/src/uncore/uart_apb.sv | 2 +- pipelined/src/uncore/uncore.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/src/wally/wallypipelinedsocwrapper.v | 2 +- 179 files changed, 179 insertions(+), 179 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 23a90db26..62fc3a1d3 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -6,7 +6,7 @@ // // Purpose: Storage for data and meta data. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 36005e4e3..3cabf059b 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -6,7 +6,7 @@ // Tested for Powers of 2. // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 657f1f97f..4abbe59a2 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4d25b8d3d..10bb4cfa0 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -6,7 +6,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 6a317e134..0219e259a 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 6263f4972..e3d845475 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index 98134afee..0ebcd3b32 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/amoalu.sv b/pipelined/src/ebu/amoalu.sv index 5e1dd8505..7bdbbc86a 100644 --- a/pipelined/src/ebu/amoalu.sv +++ b/pipelined/src/ebu/amoalu.sv @@ -6,7 +6,7 @@ // // Purpose: Performs AMO operations // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 38b0b8ffa..ed7d34599 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 41be2d2d0..f01678c78 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/controllerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv index d84add27e..3bbda0ea0 100644 --- a/pipelined/src/ebu/controllerinputstage.sv +++ b/pipelined/src/ebu/controllerinputstage.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index 333da0dd8..3e44ff93e 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index c2dfa9883..e91f34d14 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 09881ff0f..5cea973de 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -7,7 +7,7 @@ // // Purpose: Floating-point comparison unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 1363d18e5..4d156666a 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index a47031a76..2fecf769f 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index e5f58b6b6..8d881d209 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index c4cd39183..ae642890e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 863a76037..4572ba94d 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 4649e9a5b..476a7c904 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index a21754516..9a50679a6 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 4a1d7d133..94b7c043f 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 2fa3fb988..83d3c09de 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index fce047158..316e885b8 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index ef725d977..ee5e63a24 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index 4751db294..104884fc4 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index c4e341d00..48d34972e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a7f3f214c..93e809ae1 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 04b36c446..46289cd2b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 01b30eb0e..5c2168c21 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 281f74601..03678ace0 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 711502555..23e6710f1 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index cd899ebda..7f1487f24 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv index a043df7d4..df5080a74 100644 --- a/pipelined/src/fpu/fma/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -7,7 +7,7 @@ // // Purpose: FMA alginment shift // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv index dfb31dc4b..4521d4753 100644 --- a/pipelined/src/fpu/fma/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv index b9065f056..5571b2ab0 100644 --- a/pipelined/src/fpu/fma/fmalza.sv +++ b/pipelined/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv index 5f30c1666..911f6645e 100644 --- a/pipelined/src/fpu/fma/fmamult.sv +++ b/pipelined/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv index 2664d6c54..b9c61ae24 100644 --- a/pipelined/src/fpu/fma/fmasign.sv +++ b/pipelined/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index d9c82e9b5..567b2e0b9 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 393d25b14..4d774bcca 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index 4c2f14469..4dc07a975 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv index 8b6dc0263..7069cb532 100644 --- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv +++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index e2601211c..b98f749f1 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv index d8cd47b71..587c1ce53 100644 --- a/pipelined/src/fpu/postproc/flags.sv +++ b/pipelined/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 3335b40f7..dd1fb11bc 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv index 133ed977e..cbca322a2 100644 --- a/pipelined/src/fpu/postproc/negateintres.sv +++ b/pipelined/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv index 95024c777..541c703ba 100644 --- a/pipelined/src/fpu/postproc/normshift.sv +++ b/pipelined/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index c4dcf9f3f..1e8b9aec3 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv index 484d21326..d260e549f 100644 --- a/pipelined/src/fpu/postproc/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv index b14d39be0..04cd17677 100644 --- a/pipelined/src/fpu/postproc/round.sv +++ b/pipelined/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv index 0d376e7dd..9bc7c1083 100644 --- a/pipelined/src/fpu/postproc/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation ofr rounding // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv index 0f1e6bd1b..673f7cd92 100644 --- a/pipelined/src/fpu/postproc/shiftcorrection.sv +++ b/pipelined/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv index 6e9e2156e..32f8692c2 100644 --- a/pipelined/src/fpu/postproc/specialcase.sv +++ b/pipelined/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 20fb8ed25..be914fcf8 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 14a414753..f92c2be4b 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/adder.sv b/pipelined/src/generic/adder.sv index b5439a426..b9b2b2af5 100644 --- a/pipelined/src/generic/adder.sv +++ b/pipelined/src/generic/adder.sv @@ -6,7 +6,7 @@ // // Purpose: Adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/aplusbeq0.sv b/pipelined/src/generic/aplusbeq0.sv index 8dea1143f..4b3c4439d 100644 --- a/pipelined/src/generic/aplusbeq0.sv +++ b/pipelined/src/generic/aplusbeq0.sv @@ -6,7 +6,7 @@ // // Purpose: Determine if A+B = 0. Used in FP divider. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/arrs.sv b/pipelined/src/generic/arrs.sv index 3930314b5..8256d9d3e 100644 --- a/pipelined/src/generic/arrs.sv +++ b/pipelined/src/generic/arrs.sv @@ -9,7 +9,7 @@ // arrs takes in the asynchronous reset and outputs an asynchronous // rising edge, but then syncs the falling edge to the posedge clk. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/binencoder.sv b/pipelined/src/generic/binencoder.sv index f62d2aee4..a7e8061fe 100644 --- a/pipelined/src/generic/binencoder.sv +++ b/pipelined/src/generic/binencoder.sv @@ -5,7 +5,7 @@ // // Purpose: one-hot to binary encoding. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/clockgater.sv b/pipelined/src/generic/clockgater.sv index b3c2c689a..486ea4564 100644 --- a/pipelined/src/generic/clockgater.sv +++ b/pipelined/src/generic/clockgater.sv @@ -6,7 +6,7 @@ // // Purpose: Clock gater model. Must use standard cell for synthesis. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/counter.sv b/pipelined/src/generic/counter.sv index 18e27884f..06df8be63 100644 --- a/pipelined/src/generic/counter.sv +++ b/pipelined/src/generic/counter.sv @@ -6,7 +6,7 @@ // // Purpose: Counter with reset and enable // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/csa.sv b/pipelined/src/generic/csa.sv index cffef4321..ecb0f3762 100644 --- a/pipelined/src/generic/csa.sv +++ b/pipelined/src/generic/csa.sv @@ -6,7 +6,7 @@ // // Purpose: 3:2 carry-save adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv index de1df16d2..bfc9d3b55 100644 --- a/pipelined/src/generic/decoder.sv +++ b/pipelined/src/generic/decoder.sv @@ -6,7 +6,7 @@ // // Purpose: Binary encoding to one-hot decoder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv index 979c81b11..14b09899b 100644 --- a/pipelined/src/generic/flop/flop.sv +++ b/pipelined/src/generic/flop/flop.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv index 8f447b91f..5987222dd 100644 --- a/pipelined/src/generic/flop/flopen.sv +++ b/pipelined/src/generic/flop/flopen.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv index db79567a3..b01c5b5b6 100644 --- a/pipelined/src/generic/flop/flopenl.sv +++ b/pipelined/src/generic/flop/flopenl.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv index bd733aece..74cea0cdc 100644 --- a/pipelined/src/generic/flop/flopenr.sv +++ b/pipelined/src/generic/flop/flopenr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv index 197c55915..85fb09bd3 100644 --- a/pipelined/src/generic/flop/flopenrc.sv +++ b/pipelined/src/generic/flop/flopenrc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopens.sv b/pipelined/src/generic/flop/flopens.sv index 872d34900..257d28085 100644 --- a/pipelined/src/generic/flop/flopens.sv +++ b/pipelined/src/generic/flop/flopens.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv index 1fe42277b..d3296d926 100644 --- a/pipelined/src/generic/flop/flopr.sv +++ b/pipelined/src/generic/flop/flopr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/floprc.sv b/pipelined/src/generic/flop/floprc.sv index 6d084d6c4..995cff602 100644 --- a/pipelined/src/generic/flop/floprc.sv +++ b/pipelined/src/generic/flop/floprc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv index 6e208e95b..d5594c99b 100644 --- a/pipelined/src/generic/flop/synchronizer.sv +++ b/pipelined/src/generic/flop/synchronizer.sv @@ -6,7 +6,7 @@ // // Purpose: Two-stage flip-flop synchronizer // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index 5a58cf42c..54372f8df 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -5,7 +5,7 @@ // // Purpose: Leading Zero Counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 374a9a0b2..6e24c4179 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index ee66e333b..db5718a84 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -16,7 +16,7 @@ // example // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index cc23b252d..9dc3ed47c 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 6f6533a6c..90bb87f9e 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -5,7 +5,7 @@ // // Purpose: Single-ported ROM // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mux.sv b/pipelined/src/generic/mux.sv index d4f926673..c3f0e5f99 100644 --- a/pipelined/src/generic/mux.sv +++ b/pipelined/src/generic/mux.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/neg.sv b/pipelined/src/generic/neg.sv index f7947ce66..66be9e073 100644 --- a/pipelined/src/generic/neg.sv +++ b/pipelined/src/generic/neg.sv @@ -6,7 +6,7 @@ // // Purpose: 2's complement negator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/onehotdecoder.sv b/pipelined/src/generic/onehotdecoder.sv index f10519691..3c45a7622 100644 --- a/pipelined/src/generic/onehotdecoder.sv +++ b/pipelined/src/generic/onehotdecoder.sv @@ -6,7 +6,7 @@ // // Purpose: Bin to one hot decoder. Power of 2 only. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/or_rows.sv b/pipelined/src/generic/or_rows.sv index 7f892f764..f281cde59 100644 --- a/pipelined/src/generic/or_rows.sv +++ b/pipelined/src/generic/or_rows.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv index 1aa28c889..51c155c1d 100644 --- a/pipelined/src/generic/priorityonehot.sv +++ b/pipelined/src/generic/priorityonehot.sv @@ -16,7 +16,7 @@ // in 01011101010100000 // out 00000000000100000 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv index 0e2ba7dcc..3054298a5 100644 --- a/pipelined/src/generic/prioritythermometer.sv +++ b/pipelined/src/generic/prioritythermometer.sv @@ -12,7 +12,7 @@ // in 01011101010100000 // out 00000000000011111 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index d99cf3941..7d4aa9d20 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 041712a7d..430af3d80 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index 579f2c9c6..27226a6ad 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -6,7 +6,7 @@ // // Purpose: Branch comparison // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index d6a204b0d..abc86da68 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -6,7 +6,7 @@ // // Purpose: Top level controller module // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 159d07f6e..0e3e2e81a 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -6,7 +6,7 @@ // // Purpose: Wally Integer Datapath // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index feb7f9fbd..74b6acdfd 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -6,7 +6,7 @@ // // Purpose: // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index 11fb44181..c76b2355d 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -6,7 +6,7 @@ // // Purpose: Determine datapath forwarding // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 9f4a773d6..9d6d81d46 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 8ac09a911..1680d5bcc 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3-port register file // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 21573c6c7..015cc7808 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index 592d0f6fd..d15dae6ce 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -9,7 +9,7 @@ // Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want // to encode to reduce storage), valid, target PC. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv index b7fbbc5a5..2fb98417f 100644 --- a/pipelined/src/ifu/RAsPredictor.sv +++ b/pipelined/src/ifu/RAsPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index deae5cec6..246a52428 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -9,7 +9,7 @@ // Purpose: Branch prediction unit // Produces a branch prediction based on branch history. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/decompress.sv b/pipelined/src/ifu/decompress.sv index 044095f8e..aec215f6f 100644 --- a/pipelined/src/ifu/decompress.sv +++ b/pipelined/src/ifu/decompress.sv @@ -6,7 +6,7 @@ // // Purpose: Expand 16-bit compressed instructions to 32 bits // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/foldedgshare.sv index 2665f318c..38e0fe610 100644 --- a/pipelined/src/ifu/foldedgshare.sv +++ b/pipelined/src/ifu/foldedgshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index cf97039c9..92a3f9a1a 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/globalhistory.sv index d4f234ac6..86c48f6b5 100644 --- a/pipelined/src/ifu/globalhistory.sv +++ b/pipelined/src/ifu/globalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/gshare.sv index 2fbac5c57..ca801a27c 100644 --- a/pipelined/src/ifu/gshare.sv +++ b/pipelined/src/ifu/gshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index d88ccdf54..464e0f1cf 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -7,7 +7,7 @@ // Purpose: Instrunction Fetch Unit // PC, branch prediction, instruction cache // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index ef9284317..3e7e46337 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple instruction ROM -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 7e61d8c3f..1709772dd 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/oldgsharepredictor.sv index 627d2c336..29a622517 100644 --- a/pipelined/src/ifu/oldgsharepredictor.sv +++ b/pipelined/src/ifu/oldgsharepredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/oldgsharepredictor2.sv index 047e9e6b9..679358e37 100644 --- a/pipelined/src/ifu/oldgsharepredictor2.sv +++ b/pipelined/src/ifu/oldgsharepredictor2.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/satCounter2.sv index 1a0d5a276..514a29564 100644 --- a/pipelined/src/ifu/satCounter2.sv +++ b/pipelined/src/ifu/satCounter2.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit starting counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv index 7a099e74e..6a4e3da04 100644 --- a/pipelined/src/ifu/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/speculativeglobalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv index 0febd925e..943a1b785 100644 --- a/pipelined/src/ifu/speculativegshare.sv +++ b/pipelined/src/ifu/speculativegshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 7835fc00c..3cf6ea941 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -8,7 +8,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index a7d2669a3..3e41dfc4e 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index c61acd991..62a4e945e 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -6,7 +6,7 @@ // // Purpose: atomic data path. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 6e4689ef5..3ad107ae0 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple memory with bus or cache. -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv index 1b3497fa8..46a478715 100644 --- a/pipelined/src/lsu/endianswap.sv +++ b/pipelined/src/lsu/endianswap.sv @@ -6,7 +6,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index f4a4b9ffe..b14261161 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -7,7 +7,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index daf203f8e..2c7fd8d94 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -8,7 +8,7 @@ // Top level of the memory-stage core logic // Contains data cache, DTLB, subword read/write datapath, interface to external bus // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index 2b8854e5e..0a31408ad 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -6,7 +6,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 576079555..85b6bc50b 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -6,7 +6,7 @@ // // Purpose: Masking and muxing for subword writes // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv index 433a5c91f..3cbde9544 100644 --- a/pipelined/src/lsu/swbytemask.sv +++ b/pipelined/src/lsu/swbytemask.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoring.sv b/pipelined/src/mdu/intdivrestoring.sv index 59ecbe7d6..dab3c2d97 100644 --- a/pipelined/src/mdu/intdivrestoring.sv +++ b/pipelined/src/mdu/intdivrestoring.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/pipelined/src/mdu/intdivrestoringstep.sv index b37afd543..95a26e82f 100644 --- a/pipelined/src/mdu/intdivrestoringstep.sv +++ b/pipelined/src/mdu/intdivrestoringstep.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mdu.sv b/pipelined/src/mdu/mdu.sv index 0490642c6..bb242b75f 100644 --- a/pipelined/src/mdu/mdu.sv +++ b/pipelined/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mul.sv b/pipelined/src/mdu/mul.sv index a8c4e2966..b94ce7993 100644 --- a/pipelined/src/mdu/mul.sv +++ b/pipelined/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Multiply instructions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdec.sv b/pipelined/src/mmu/adrdec.sv index 6c0303cca..0d8248f26 100644 --- a/pipelined/src/mmu/adrdec.sv +++ b/pipelined/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 8dc9c45cc..4df5187d2 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 67e4a83ba..d155e6c75 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -11,7 +11,7 @@ // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index 1949bf133..f36ae7de4 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index f74cff2a1..367fef39d 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv index fb3e2c614..0eaf623d5 100644 --- a/pipelined/src/mmu/pmpadrdec.sv +++ b/pipelined/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv index c6f357a69..ae3f03e6d 100644 --- a/pipelined/src/mmu/pmpchecker.sv +++ b/pipelined/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlb.sv b/pipelined/src/mmu/tlb.sv index 7d5e51bbe..d80fe2bbb 100644 --- a/pipelined/src/mmu/tlb.sv +++ b/pipelined/src/mmu/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv index 79a1f21e9..8f21e13a3 100644 --- a/pipelined/src/mmu/tlbcam.sv +++ b/pipelined/src/mmu/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcamline.sv b/pipelined/src/mmu/tlbcamline.sv index 627f496dc..44db71fa4 100644 --- a/pipelined/src/mmu/tlbcamline.sv +++ b/pipelined/src/mmu/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index eb0735130..8821ccf2e 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index ee5ac7fe6..92c4a97b3 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbmixer.sv b/pipelined/src/mmu/tlbmixer.sv index 71e5ca917..2e6f5860d 100644 --- a/pipelined/src/mmu/tlbmixer.sv +++ b/pipelined/src/mmu/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbram.sv b/pipelined/src/mmu/tlbram.sv index 8b2c59d68..fd891940d 100644 --- a/pipelined/src/mmu/tlbram.sv +++ b/pipelined/src/mmu/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbramline.sv b/pipelined/src/mmu/tlbramline.sv index 6c3a30790..bfad0d7b7 100644 --- a/pipelined/src/mmu/tlbramline.sv +++ b/pipelined/src/mmu/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/vm64check.sv b/pipelined/src/mmu/vm64check.sv index ad4ff4cea..39ff328e3 100644 --- a/pipelined/src/mmu/vm64check.sv +++ b/pipelined/src/mmu/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 003e5bf47..52f277f3f 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 427c8152f..6b2497d4a 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -9,7 +9,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 9d0c6aff5..73a7fa025 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 1d621da9d..d100285cd 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -8,7 +8,7 @@ // Purpose: Machine-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index d9590d0f8..2f9d8e49b 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 705052975..82e8b5d5d 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 0bf35694b..3bc02de38 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -8,7 +8,7 @@ // See RISC-V Privileged Mode Specification 20190608 Table 2.2 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index d2729e9f1..30838638c 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index edaca1da4..73ecfada5 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index 1eb6b4dbb..6ce4e9107 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -7,7 +7,7 @@ // Purpose: Track privilege mode // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv index 52761855c..6ba6b3ba0 100644 --- a/pipelined/src/privileged/privpiperegs.sv +++ b/pipelined/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 05f1f6e97..95ceddb6b 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -7,7 +7,7 @@ // Purpose: Handle Traps: Exceptions and Interrupts // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv index 2a3656955..9c72d1f52 100644 --- a/pipelined/src/uncore/ahbapbbridge.sv +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index e80be7d7c..679d2c8e8 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv index f84707a84..1cc33f07f 100644 --- a/pipelined/src/uncore/gpio_apb.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -8,7 +8,7 @@ // See FE310-G002-Manual-v19p05 for specifications // No interrupts, drive strength, or pull-ups supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index bf5803346..c39c0329e 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -13,7 +13,7 @@ // Do we detect requests as level-triggered or edge-trigged? // If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests? // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index 2a0a1b3ff..1834f21b9 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core, with AHB interface // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv index 9aba4d68d..72bfbe715 100644 --- a/pipelined/src/uncore/rom_ahb.sv +++ b/pipelined/src/uncore/rom_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip ROM, external to core // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index f756e45e1..b8c5cfdee 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -6,7 +6,7 @@ // // Purpose: SDC interface to AHBLite BUS. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv index 8009790f2..e6107c041 100644 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ b/pipelined/src/uncore/sdc/SDCcounter.sv @@ -7,7 +7,7 @@ // // Purpose: basic up counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv index 44f582571..d475b395f 100644 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ b/pipelined/src/uncore/sdc/clkdivider.sv @@ -7,7 +7,7 @@ // // Purpose: clock divider for sd flash // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv index 4cc43211a..6baabdba1 100644 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv @@ -8,7 +8,7 @@ // Purpose: CRC16 generator SIPO using register_ce // w/o appending any zero-bits to the message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv index 797e62f64..a2dc06fc4 100644 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ b/pipelined/src/uncore/sdc/crc7_pipo.sv @@ -9,7 +9,7 @@ // clock cycle! // w/o appending any zero-bits to the message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv index 8f7fb928e..3a52b5c41 100644 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv @@ -7,7 +7,7 @@ // Purpose: CRC7 generator SIPO using register_ce // w/o appending any zero-bits othe message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv index 2d332b435..f134212c5 100644 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv @@ -5,7 +5,7 @@ // Modified: Ross Thompson September 18, 2021 // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv index 1956cbc7a..e63188377 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv index d08179728..bd050c4e5 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv index 327a833cd..6ec8ada13 100644 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv @@ -15,7 +15,7 @@ // It must be synchronized with 50 MHz and held for a minimum period of a full // 400 KHz pulse width. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv index b1b4a163d..4769e6eaa 100644 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv @@ -6,7 +6,7 @@ // // Purpose: Finite state machine for the SD CMD bus // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv index 49ba94bf1..476687523 100644 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv @@ -8,7 +8,7 @@ // bus of the SD card. // 14 State Mealy FSM + Safe state = 15 State Mealy FSM // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv index 7a9c35fa6..90ae706ae 100644 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ b/pipelined/src/uncore/sdc/sd_top.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv index 0e6afa75c..ad04877e0 100644 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ b/pipelined/src/uncore/sdc/simple_timer.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv index ed55559dc..54f513c31 100644 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv @@ -9,7 +9,7 @@ // bit first. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv index 894df3696..685f74084 100644 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ b/pipelined/src/uncore/sdc/up_down_counter.sv @@ -6,7 +6,7 @@ // // Purpose: basic up counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index f627aca89..3217c3c67 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not ye implemented*** // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index f1d6fd7a6..d5389bb32 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model *** // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 1ca9d3cb4..7a6c3dc08 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index b6d04b62c..6954a9da9 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 69c3ce04e..066cecb25 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index a812924c6..33e454f33 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University //