diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv
index 7c042886a..3c552b371 100644
--- a/src/lsu/endianswap.sv
+++ b/src/lsu/endianswap.sv
@@ -34,7 +34,43 @@ module endianswap #(parameter LEN) (
   output logic [LEN-1:0]  y
 ); 
 
-  if(LEN == 128) begin
+  if(LEN == 256) begin
+    always_comb 
+      if (BigEndianM) begin // swap endianness
+        y[255:248] = a[7:0];
+        y[247:240] = a[15:8];
+        y[239:232] = a[23:16];
+        y[231:224] = a[31:24];
+        y[223:216] = a[39:32];
+        y[215:208] = a[47:40];
+        y[207:200] = a[55:48];
+        y[199:192] = a[63:56];
+        y[191:184] = a[71:64];
+        y[183:176] = a[79:72];
+        y[175:168] = a[87:80];
+        y[167:160] = a[95:88];
+        y[159:152] = a[103:96];
+        y[151:144] = a[111:104];
+        y[143:136] = a[119:112];
+        y[135:128] = a[127:120];
+        y[127:120] = a[135:128];
+        y[119:112] = a[142:136];
+        y[111:104] = a[152:144];
+        y[103:96]  = a[159:152];
+        y[95:88]   = a[167:160];
+        y[87:80]   = a[175:168];
+        y[79:72]   = a[183:176];
+        y[71:64]   = a[191:184];
+        y[63:56]   = a[199:192];
+        y[55:48]   = a[207:200];
+        y[47:40]   = a[215:208];
+        y[39:32]   = a[223:216];
+        y[31:24]   = a[231:224];
+        y[23:16]   = a[239:232];
+        y[15:8]    = a[247:240];
+        y[7:0]     = a[255:248];
+      end else y = a;
+  end else if(LEN == 128) begin
     always_comb 
       if (BigEndianM) begin // swap endianness
         y[127:120] = a[7:0];
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 567dbdb79..896af0b46 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -450,8 +450,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if (P.BIGENDIAN_SUPPORTED) begin:endian
-    endianswapdouble #(MLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-    endianswapdouble #(MLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+    endianswap #(MLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+    endianswap #(MLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
   end else begin
     assign LSUWriteDataM = LittleEndianWriteDataM;
     assign LittleEndianReadDataWordM = ReadDataWordMuxM;
diff --git a/src/lsu/subworddreadmisaligned.sv b/src/lsu/subworddreadmisaligned.sv
index 66ca0375e..2868a54d8 100644
--- a/src/lsu/subworddreadmisaligned.sv
+++ b/src/lsu/subworddreadmisaligned.sv
@@ -77,7 +77,7 @@ module subwordreadmisaligned #(parameter LLEN)
       3'b001:  ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};                                              // lh/flh
       3'b010:  ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};                                                      // lw/flw
       3'b011:  if(LLEN == 128 || LLEN == 64 ) ReadDataM = {{LLEN-64{ReadDataAlignedM[63]|FpLoadStoreM}}, ReadDataAlignedM[63:0]}; // ld/fld
-      3'b100:  if(LLEN == 128) ReadDataM = FpLoadStoreM ? ReadDataAlignedM[LLEN-1:0] : {{LLEN-8{1'b0}}, ByteM[7:0]};              // lbu/flq   - only needed when LLEN=128
+      3'b100:  if(LLEN == 128) ReadDataM = FpLoadStoreM ? ReadDataAlignedM[LLEN-1:0] : {{LLEN-8{1'b0}}, ByteM[7:0]};              // lbu/flq
           else if(LLEN == 64) ReadDataM = FpLoadStoreM ? ReadDataAlignedM[LLEN-1:0] : {{LLEN-8{1'b0}}, ByteM[7:0]};
       3'b101:  ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]};                                                                    // lhu
       3'b110:  ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]};                                                                        // lwu