diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index 12967764f..61bf461eb 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -95,16 +95,13 @@ localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
 
 // intermediate division parameters not directly used in Divider
 localparam FPDIVN      = NF+3; // length of floating-point inputs: Ns + 2 = Nf + 3 for 1 integer bit, Nf fracitonal bits, 2 extra bits to shift sqrt into [1/4, 1)]
-localparam DIVN        = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN+3; // standard length of input: max(XLEN, NF+2) ***
+localparam DIVN        = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // standard length of input: max(XLEN, NF+2) ***
 
 // division constants
-
-// *** define NF+2, justify, use in DIVN
 localparam LOGR        = $clog2(RADIX);                             // r = log(R)
 localparam RK          = LOGR*DIVCOPIES;                            // r*k bits per cycle generated
-//localparam FPDUR       = (DIVN+1)/RK + 1 + (RADIX/4);               // *** relate to algorithm for rest of these
-localparam FPDUR       = (DIVN+LOGR-1)/RK + 1 ;               // ceiling((DIVN+LOGR)/RK)
-localparam DURLEN      = $clog2(FPDUR+1);
+localparam FPDUR       = (DIVN+LOGR-1)/RK + 1 ;                     // ceiling((n+r)/rk)
+localparam DURLEN      = $clog2(FPDUR+1);                           // number of bits to represent the duration
 localparam DIVb        = FPDUR*RK - 1; // canonical fdiv size (b)
 localparam DIVBLEN     = $clog2(DIVb+2)-1;                          // *** where is 2 coming from?
 
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index e5f215e07..5ef752691 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -115,8 +115,8 @@ module testbenchfp;
    logic 			FlushE;
    logic 			IFDivStartE;
    logic 			FDivDoneE;
-   logic [P.NE+1:0] 		QeM;
-   logic [P.DIVb:0] 		QmM;
+   logic [P.NE+1:0] 		UeM;
+   logic [P.DIVb:0] 		UmM;
    logic [P.XLEN-1:0] 		FIntDivResultM;
    logic 			ResMatch;                   // Check if result match
    logic 			FlagMatch;                  // Check if IEEE flags match
@@ -705,7 +705,7 @@ module testbenchfp;
    end
    
    postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
-				.OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
+				.OpCtrl(OpCtrlVal), .DivUm(Quot), .DivUe(DivCalcExp),
 				.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
 				.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
 				.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
@@ -734,8 +734,8 @@ module testbenchfp;
 			     .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
 			     .XNaNE(XNaN), .YNaNE(YNaN), 
 			     .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
-			     .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
-			     .QmM(Quot),
+			     .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .UeM(DivCalcExp),
+			     .UmM(Quot),
 			     .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
 			     .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
 			     .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));