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fixed some bugs with the RAS.

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This commit is contained in:
Ross Thompson 2021-03-30 13:57:40 -05:00
parent cdb7d15709
commit a3925505bf
4 changed files with 22 additions and 21 deletions
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6
wally-pipelined/src/ifu/BTBPredictor.sv
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@ -36,7 +36,7 @@ module BTBPredictor
input logic StallF, StallD, StallE, FlushF, FlushD, FlushE, input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [`XLEN-1:0] TargetPC, output logic [`XLEN-1:0] TargetPC,
output logic [3:0] InstrClass, output logic [4:0] InstrClass,
output logic Valid, output logic Valid,
// update // update
input logic UpdateEN, input logic UpdateEN,
@ -108,7 +108,7 @@ module BTBPredictor
// Another optimization may be using a PC relative address. // Another optimization may be using a PC relative address.
// *** need to add forwarding. // *** need to add forwarding.
SRAM2P1R1W #(Depth, `XLEN+4) memory(.clk(clk), SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk),
.reset(reset), .reset(reset),
.RA1(LookUpPCIndex), .RA1(LookUpPCIndex),
.RD1({{InstrClass, TargetPC}}), .RD1({{InstrClass, TargetPC}}),
@ -116,7 +116,7 @@ module BTBPredictor
.WA1(UpdatePCIndex), .WA1(UpdatePCIndex),
.WD1({UpdateInstrClass, UpdateTarget}), .WD1({UpdateInstrClass, UpdateTarget}),
.WEN1(UpdateEN), .WEN1(UpdateEN),
.BitWEN1({4'b1111, {`XLEN{1'b1}}})); // *** definitely not right. .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
endmodule endmodule

6
wally-pipelined/src/ifu/bpred.sv
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@ -47,7 +47,7 @@ module bpred
input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken. input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken.
input logic [`XLEN-1:0] PCD, // The address the branch predictor took. input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
input logic [3:0] InstrClassE, input logic [4:0] InstrClassE,
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE output logic BPPredWrongE
); );
@ -55,7 +55,7 @@ module bpred
logic BTBValidF; logic BTBValidF;
logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE; logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE;
logic [3:0] BPInstrClassF, BPInstrClassD, BPInstrClassE; logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE;
logic [`XLEN-1:0] BTBPredPCF, RASPCF; logic [`XLEN-1:0] BTBPredPCF, RASPCF;
logic TargetWrongE; logic TargetWrongE;
logic FallThroughWrongE; logic FallThroughWrongE;
@ -146,7 +146,7 @@ module bpred
.reset(reset), .reset(reset),
.pop(BPInstrClassF[3] & ~StallF), .pop(BPInstrClassF[3] & ~StallF),
.popPC(RASPCF), .popPC(RASPCF),
.push(InstrClassE[3] & ~StallE), .push(InstrClassE[4] & ~StallE),
.incr(1'b0), .incr(1'b0),
.pushPC(PCLinkE)); .pushPC(PCLinkE));

11
wally-pipelined/src/ifu/ifu.sv
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@ -86,7 +86,7 @@ module ifu (
// branch predictor signals // branch predictor signals
logic SelBPPredF; logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F; logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F;
logic [3:0] InstrClassD, InstrClassE; logic [4:0] InstrClassD, InstrClassE;
// *** put memory interface on here, InstrF becomes output // *** put memory interface on here, InstrF becomes output
@ -173,8 +173,9 @@ module ifu (
// the branch predictor needs a compact decoding of the instruction class. // the branch predictor needs a compact decoding of the instruction class.
// *** consider adding in the alternate return address x5 for returns. // *** consider adding in the alternate return address x5 for returns.
assign InstrClassD[3] = InstrD[6:0] == 7'h67 && InstrD[19:15] == 5'h01; // return assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 && InstrD[19:15] != 5'h01; // jump register, but not return assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must link to ra or r5
assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // jump register, but not return
assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
@ -201,14 +202,14 @@ module ifu (
flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later
flopenrc #(4) InstrClassRegE(.clk(clk), flopenrc #(5) InstrClassRegE(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.clear(FlushE), .clear(FlushE),
.d(InstrClassD), .d(InstrClassD),
.q(InstrClassE)); .q(InstrClassE));
flopenrc #(4) InstrClassRegM(.clk(clk), flopenrc #(5) InstrClassRegM(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallM), .en(~StallM),
.clear(FlushM), .clear(FlushM),

20
wally-pipelined/testbench/testbench-busybear.sv
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@ -39,7 +39,7 @@ module testbench_busybear();
// read pc trace file // read pc trace file
integer data_file_PC, scan_file_PC; integer data_file_PC, scan_file_PC;
initial begin initial begin
data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); data_file_PC = $fopen("../../../busybear_boot/parsedPC.txt", "r");
if (data_file_PC == 0) begin if (data_file_PC == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -48,7 +48,7 @@ module testbench_busybear();
integer data_file_PCW, scan_file_PCW; integer data_file_PCW, scan_file_PCW;
initial begin initial begin
data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r"); data_file_PCW = $fopen("../../../busybear_boot/parsedPC.txt", "r");
if (data_file_PCW == 0) begin if (data_file_PCW == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -58,7 +58,7 @@ module testbench_busybear();
// read register trace file // read register trace file
integer data_file_rf, scan_file_rf; integer data_file_rf, scan_file_rf;
initial begin initial begin
data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r"); data_file_rf = $fopen("../../../busybear_boot/parsedRegs.txt", "r");
if (data_file_rf == 0) begin if (data_file_rf == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -68,7 +68,7 @@ module testbench_busybear();
// read CSR trace file // read CSR trace file
integer data_file_csr, scan_file_csr; integer data_file_csr, scan_file_csr;
initial begin initial begin
data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r"); data_file_csr = $fopen("../../../busybear_boot/parsedCSRs.txt", "r");
if (data_file_csr == 0) begin if (data_file_csr == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -78,7 +78,7 @@ module testbench_busybear();
// read memreads trace file // read memreads trace file
integer data_file_memR, scan_file_memR; integer data_file_memR, scan_file_memR;
initial begin initial begin
data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r"); data_file_memR = $fopen("../../../busybear_boot/parsedMemRead.txt", "r");
if (data_file_memR == 0) begin if (data_file_memR == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -88,7 +88,7 @@ module testbench_busybear();
// read memwrite trace file // read memwrite trace file
integer data_file_memW, scan_file_memW; integer data_file_memW, scan_file_memW;
initial begin initial begin
data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r"); data_file_memW = $fopen("../../../busybear_boot/parsedMemWrite.txt", "r");
if (data_file_memW == 0) begin if (data_file_memW == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -97,10 +97,10 @@ module testbench_busybear();
// initial loading of memories // initial loading of memories
initial begin initial begin
$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); $readmemh("../../../busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM); $readmemh("../../../busybear_boot/ram.txt", dut.uncore.dtim.RAM);
$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); $readmemh("../../../busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3);
$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM); $readmemh("../../../busybear_boot/ram.txt", dut.imem.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
end end