From a38f7cc8a10e830ef0c41ad6bede60b9fa0d4f2c Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 23 Feb 2023 13:45:44 -0800 Subject: [PATCH] added reset values to stime and stimecmp registers --- src/privileged/csrs.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 253d02457..e47a44426 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -102,10 +102,10 @@ module csrs #(parameter flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (`SSTC_SUPPORTED) begin if (`XLEN == 64) - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); else begin - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); - flopenr #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); + flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); end end else assign STIMECMP_REGW = 0;