From a35fb3addd99370d8a6020cd9d5aca3adbb1c7a6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 8 Jan 2023 23:35:02 -0600 Subject: [PATCH] core part of global history works now. forwarding is still broken. --- pipelined/config/rv64gc/wally-config.vh | 3 +- pipelined/regression/wave.do | 75 +++++++------- pipelined/src/ifu/bpred.sv | 2 +- pipelined/src/ifu/speculativeglobalhistory.sv | 99 ++++++++++--------- tests/custom/simple/global_hist_test.s | 36 +++++++ tests/custom/simple/header.h | 1 + tests/custom/simple/main.c | 1 + 7 files changed, 136 insertions(+), 81 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index a7d0f34d9..70ce1938d 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -135,7 +135,8 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPOLDGSHARE2" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE +//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index d9a751586..92804e29f 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -84,27 +84,27 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -expand -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC +add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F @@ -163,7 +163,6 @@ add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURSTD add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST @@ -363,7 +362,6 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmach add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM @@ -586,18 +584,27 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewGHRF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPInstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {2086 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {9616 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -613,4 +620,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1919 ns} {2207 ns} +WaveRestoreZoom {9519 ns} {9917 ns} diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index e83ae761a..a08ef3190 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -97,7 +97,7 @@ module bpred ( .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + speculativeglobalhistory #(5) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(BPInstrClassF[0]), .BranchInstrD(BPInstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .PCSrcE); diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv index ac4753669..dda1415dd 100644 --- a/pipelined/src/ifu/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/speculativeglobalhistory.sv @@ -48,41 +48,51 @@ module speculativeglobalhistory input logic PCSrcE ); - logic MatchD, MatchE, MatchM, MatchW, MatchX, MatchXF; -// logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW; - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW, NewDirPredictionX, NewDirPredictionXF; + logic MatchF, MatchD, MatchE, MatchM, MatchW; + logic MatchNextX, MatchXF; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHRW, GHRNextF, GHRCurrentF, GHRCurrentE; - logic [k-1:0] NewGHRF, NewGHRD, NewGHRE, NewGHRM, NewGHRW; + logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; + logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW; + + logic [k-1:0] GHRF; + logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; + + logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; + ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), - .ra1(NewGHRF), + .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), + .ra1(GHRNextF), .rd1(TableDirPredictionF), - .wa2(GHRM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(GHRW[k-1:0]), + .wd2(NewDirPredictionW), + .we2(BranchInstrW & ~StallW & ~FlushW), .bwe2(1'b1)); - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the demi stage NextF and then - // register for use in the Fetch stage. - assign MatchD = BranchInstrD & (GHRD == GHRF); - assign MatchE = BranchInstrE & (GHRE == GHRF); - assign MatchM = BranchInstrM & (GHRM == GHRF); - assign MatchW = BranchInstrW & (GHRW == GHRF); - assign MatchX = MatchD | MatchE | MatchM | MatchW; - - assign NewDirPredictionX = MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - MatchM ? NewDirPredictionM : - MatchW ? NewDirPredictionW : '0; - flopenr #(2) NewPredXReg(clk, reset, ~StallF, NewDirPredictionX, NewDirPredictionXF); - flopenrc #(1) DoForwardReg(clk, reset, FlushD, ~StallF, MatchX, MatchXF); - - assign DirPredictionF = MatchXF ? NewDirPredictionXF : TableDirPredictionF; + // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage + // and then register for use in the Fetch stage. + assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF); + assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]); + assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]); + assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]); + assign MatchW = BranchInstrW & (GHRNextF == GHRM[k-1:0]); + assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW; + + flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); + + assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : + MatchD ? NewDirPredictionD : + MatchE ? NewDirPredictionE : + MatchM ? NewDirPredictionM : + NewDirPredictionW; + + flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); + + assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; // DirPrediction pipeline flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); @@ -94,31 +104,30 @@ module speculativeglobalhistory satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW); - // PCSrc pipeline flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); // GHR pipeline - assign GHRNextF = FlushD & BranchInstrD & ~FlushE & ~FlushM & ~FlushW ? NewGHRD : - FlushE & BranchInstrE & ~FlushM & ~FlushW ? NewGHRE : - FlushM & BranchInstrM & ~FlushW ? NewGHRM : - FlushW & BranchInstrW ? NewGHRW : - NewGHRF; - - flopenr #(k) GHRFReg(clk, reset, ~StallF, GHRNextF, GHRF); - //assign GHRF = BranchInstrF ? {NewDirPredictionF[1], GHRCurrentF[k-1:1]} : GHRCurrentF; - assign NewGHRF = BranchInstrF ? {NewDirPredictionF[1], GHRF[k-1:1]} : GHRF; - flopenr #(k) GHRDReg(clk, reset, ~StallD, GHRF, GHRD); - assign NewGHRD = BranchInstrD ? {NewDirPredictionD[1], GHRD[k-1:1]} : GHRD; - flopenr #(k) GHREReg(clk, reset, ~StallE, GHRD, GHRE); - assign NewGHRE = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE; - flopenr #(k) GHRMReg(clk, reset, ~StallM, GHRE, GHRM); - assign NewGHRM = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM; - flopenr #(k) GHRWReg(clk, reset, ~StallW, GHRM, GHRW); - assign NewGHRW = BranchInstrW ? {PCSrcW, GHRW[k-1:1]} : GHRW; + assign GHRNextF = FlushD ? GHRNextD[k:1] : + BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : + GHRF; + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + + assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF}; + flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + + assign GHRNextE = FlushE ? GHRNextM : GHRD; + flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); + assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + + assign GHRNextM = FlushM ? GHRNextW : GHRE; + flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + + assign GHRNextW = FlushW ? GHRW : GHRM; + flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; diff --git a/tests/custom/simple/global_hist_test.s b/tests/custom/simple/global_hist_test.s index 9e3bfd7b5..28e4f4ff1 100644 --- a/tests/custom/simple/global_hist_test.s +++ b/tests/custom/simple/global_hist_test.s @@ -52,6 +52,42 @@ oneLoopTest5: ret +.section .text +.globl global_hist_6_space_test +.type global_hist_6_space_test, @function +global_hist_6_space_test: + li t1, 1 + li t2, 200 + li t3, 0 + li t4, 1 + +loop_6: + # instruction + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + beqz t4, zero_6 # this branch toggles between taken and not taken. + li t4, 0 + j one_6 +zero_6: + li t4, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + add t1, t1, t4 + +one_6: + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t2, t2, -1 + bnez t2, loop_6 + + ret + .section .text .globl global_hist_4_space_test .type global_hist_4_space_test, @function diff --git a/tests/custom/simple/header.h b/tests/custom/simple/header.h index 7a1b51926..973bdd59a 100644 --- a/tests/custom/simple/header.h +++ b/tests/custom/simple/header.h @@ -10,5 +10,6 @@ void global_hist_1_space_test(); void global_hist_2_space_test(); void global_hist_3_space_test(); void global_hist_4_space_test(); +void global_hist_6_space_test(); void oneLoopTest(); #endif diff --git a/tests/custom/simple/main.c b/tests/custom/simple/main.c index 83d43e32d..bebd96f6b 100644 --- a/tests/custom/simple/main.c +++ b/tests/custom/simple/main.c @@ -3,6 +3,7 @@ int main(){ //int res = icache_spill_test(); oneLoopTest(); + global_hist_6_space_test(); global_hist_4_space_test(); global_hist_3_space_test(); global_hist_2_space_test();