mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
This commit is contained in:
parent
1c83914662
commit
a34cbdb7d0
@ -156,10 +156,13 @@ module controller(
|
||||
7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
|
||||
7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
|
||||
7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
|
||||
7'b1110011: if (Funct3D == 3'b000)
|
||||
7'b1110011: if (`ZICSR_SUPPORTED) begin
|
||||
if (Funct3D == 3'b000)
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
|
||||
else
|
||||
else
|
||||
ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
|
||||
end else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
endcase
|
||||
|
||||
|
@ -7,7 +7,7 @@ NAME := synth
|
||||
export DESIGN ?= wallypipelinedcore
|
||||
export FREQ ?= 500
|
||||
export CONFIG ?= rv32e
|
||||
export TECH ?= 130
|
||||
export TECH ?= sky130
|
||||
|
||||
time := $(shell date +%F-%H-%M)
|
||||
hash := $(shell git rev-parse --short HEAD)
|
||||
|
@ -160,7 +160,7 @@ redirect $filename {report_constraint -all_violators}
|
||||
redirect $outputDir/reports/check_design.rpt { check_design }
|
||||
|
||||
# Report Final Netlist (Hierarchical)
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".vh"]
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
|
||||
write_file -f verilog -hierarchy -output $filename
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
|
||||
|
Loading…
Reference in New Issue
Block a user