From a338089b6f89298413590eac9e93746e8c90bfd5 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sat, 25 Jan 2025 16:22:27 -0800
Subject: [PATCH] Fix FunctionName module naming
---
sim/questa/fpga-wave.do | 2 +-
testbench/common/functionName.sv | 2 +-
testbench/common/loggers.sv | 16 ++++++++--------
testbench/testbench.sv | 12 ++++++------
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/sim/questa/fpga-wave.do b/sim/questa/fpga-wave.do
index e95443fbe..ebff54cd3 100644
--- a/sim/questa/fpga-wave.do
+++ b/sim/questa/fpga-wave.do
@@ -53,7 +53,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
-add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
+add wave -noupdate -group {Execution Stage} /testbench/functionName/functionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv
index 2d257ce32..141dcd88f 100644
--- a/testbench/common/functionName.sv
+++ b/testbench/common/functionName.sv
@@ -23,7 +23,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
-module FunctionName import cvw::*; #(parameter cvw_t P) (
+module functionName import cvw::*; #(parameter cvw_t P) (
input logic reset,
input logic clk,
input string ProgramAddrMapFile,
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 1a88bc052..5ed07b6d6 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -84,11 +84,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
always_comb
if (TEST == "embench") begin
- StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
- EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
+ StartSampleFirst = functionName.functionName.FunctionName == "start_trigger";
+ EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger";
end else if (TEST == "coremark") begin
- StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
- EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+ StartSampleFirst = functionName.functionName.FunctionName == "start_time";
+ EndSampleFirst = functionName.functionName.FunctionName == "stop_time";
end else begin
StartSampleFirst = reset;
EndSampleFirst = '0;
@@ -106,22 +106,22 @@ module loggers import cvw::*; #(parameter cvw_t P,
if(TEST == "embench") begin
// embench runs warmup then runs start_trigger
// embench end with stop_trigger.
- //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
+ //assign StartSampleFirst = functionName.functionName.FunctionName == "start_trigger";
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
- //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
+ //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger";
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else if(TEST == "coremark") begin
// embench runs warmup then runs start_trigger
// embench end with stop_trigger.
- //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
+ //assign StartSampleFirst = functionName.functionName.FunctionName == "start_time";
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
- //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+ //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_time";
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index eb1c88955..194e70d6c 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -38,7 +38,7 @@ import cvw::*;
module testbench;
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
- parameter DEBUG=0;
+ parameter DEBUG=1;
parameter PrintHPMCounters=0;
parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0;
@@ -684,8 +684,8 @@ module testbench;
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
// track the current function or global label
- if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
- FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
+ if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : functionName
+ functionName #(P) functionName(.reset(reset_ext | TestBenchReset),
.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
end
@@ -710,11 +710,11 @@ module testbench;
always @(posedge clk) begin
// if (reset) PrevPCZero <= 0;
- // else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0);
+ // else if (dut.core.InstrValidM) PrevPCZero <= (functionName.PCM == 0 & dut.core.ifu.InstrM == 0);
TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
- // (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
- // if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
+ // (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
+ // if (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
// $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
end