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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Update csr.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
a1a9d668c5
commit
a2645dd576
@ -29,66 +29,66 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csr import cvw::*; #(parameter cvw_t P) (
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module csr import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic clk, reset,
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input logic FlushM, FlushW,
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input logic FlushM, FlushW,
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input logic StallE, StallM, StallW,
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input logic StallE, StallM, StallW,
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input logic [31:0] InstrM, // current instruction
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input logic [31:0] InstrM, // current instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return logic
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input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return logic
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input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
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input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic TrapM, // trap is occurring
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input logic TrapM, // trap is occurring
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input logic mretM, sretM, wfiM, // return or WFI instruction
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input logic mretM, sretM, wfiM, // return or WFI instruction
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input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
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input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
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input logic InterruptM, // interrupt is occurring
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input logic InterruptM, // interrupt is occurring
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input logic ExceptionM, // interrupt is occurring
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input logic ExceptionM, // interrupt is occurring
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input logic MTimerInt, // timer interrupt
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input logic MTimerInt, // timer interrupt
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input logic MExtInt, SExtInt, // external interrupt (from PLIC)
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input logic MExtInt, SExtInt, // external interrupt (from PLIC)
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input logic MSwInt, // software interrupt
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input logic MSwInt, // software interrupt
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input logic [63:0] MTIME_CLINT, // TIME value from CLINT
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input logic [63:0] MTIME_CLINT, // TIME value from CLINT
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input logic InstrValidM, // current instruction is valid
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input logic InstrValidM, // current instruction is valid
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input logic FRegWriteM, // writes to floating point registers change STATUS.FS
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input logic FRegWriteM, // writes to floating point registers change STATUS.FS
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input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR
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input logic [4:0] SetFflagsM, // Set floating point flag bits in FCSR
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input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode
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input logic [1:0] NextPrivilegeModeM, // STATUS bits updated based on next privilege mode
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input logic [1:0] PrivilegeModeW, // current privilege mode
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input logic [1:0] PrivilegeModeW, // current privilege mode
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input logic [3:0] CauseM, // Trap cause
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input logic [3:0] CauseM, // Trap cause
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input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode
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input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode
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// inputs for performance counters
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// inputs for performance counters
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input logic LoadStallD,
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input logic LoadStallD,
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input logic StoreStallD,
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input logic StoreStallD,
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input logic ICacheStallF,
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input logic ICacheStallF,
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input logic DCacheStallM,
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input logic DCacheStallM,
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input logic BPDirPredWrongM,
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input logic BPDirPredWrongM,
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input logic BTAWrongM,
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input logic BTAWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic IClassWrongM,
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input logic IClassWrongM,
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input logic BPWrongM, // branch predictor is wrong
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM,
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input logic [3:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic ICacheAccess,
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input logic sfencevmaM,
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input logic sfencevmaM,
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input logic InvalidateICacheM,
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input logic InvalidateICacheM,
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input logic DivBusyE, // integer divide busy
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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input logic FDivBusyE, // floating point divide busy
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// outputs from CSRs
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// outputs from CSRs
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output logic [1:0] STATUS_MPP,
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output logic [1:0] STATUS_MPP,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
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output logic [15:0] MEDELEG_REGW,
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output logic [15:0] MEDELEG_REGW,
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output logic [P.XLEN-1:0] SATP_REGW,
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output logic [P.XLEN-1:0] SATP_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
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output logic [1:0] STATUS_FS,
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output logic [1:0] STATUS_FS,
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output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
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output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
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output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],
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output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],
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output logic [2:0] FRM_REGW,
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output logic [2:0] FRM_REGW,
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//
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//
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output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
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output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
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output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
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output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
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output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
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output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
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output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
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output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
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);
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);
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localparam MIP = 12'h344;
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localparam MIP = 12'h344;
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@ -102,27 +102,27 @@ module csr import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
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logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
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logic [P.XLEN-1:0] STVEC_REGW, MTVEC_REGW;
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logic [P.XLEN-1:0] STVEC_REGW, MTVEC_REGW;
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logic [P.XLEN-1:0] MEPC_REGW, SEPC_REGW;
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logic [P.XLEN-1:0] MEPC_REGW, SEPC_REGW;
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logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
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logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
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logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
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logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
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logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
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logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
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logic UngatedCSRMWriteM;
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logic UngatedCSRMWriteM;
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logic WriteFRMM, WriteFFLAGSM;
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logic WriteFRMM, WriteFFLAGSM;
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logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
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logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
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logic [4:0] NextCauseM;
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logic [4:0] NextCauseM;
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logic [11:0] CSRAdrM;
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logic [11:0] CSRAdrM;
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logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
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logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
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logic InsufficientCSRPrivilegeM;
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logic InsufficientCSRPrivilegeM;
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logic IllegalCSRMWriteReadonlyM;
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logic IllegalCSRMWriteReadonlyM;
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logic [P.XLEN-1:0] CSRReadVal2M;
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logic [P.XLEN-1:0] CSRReadVal2M;
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logic [11:0] MIP_REGW_writeable;
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logic [11:0] MIP_REGW_writeable;
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logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
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logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
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logic MTrapM, STrapM;
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logic MTrapM, STrapM;
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logic [P.XLEN-1:0] EPC;
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logic [P.XLEN-1:0] EPC;
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logic RetM;
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logic RetM;
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logic SelMtvecM;
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logic SelMtvecM;
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logic [P.XLEN-1:0] TVecAlignedM;
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logic [P.XLEN-1:0] TVecAlignedM;
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logic InstrValidNotFlushedM;
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logic InstrValidNotFlushedM;
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logic STimerInt;
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logic STimerInt;
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// only valid unflushed instructions can access CSRs
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// only valid unflushed instructions can access CSRs
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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