From a22de456312ea45ff77612eec9a73c1eed625c2e Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sat, 2 Mar 2024 16:20:31 -0600
Subject: [PATCH] Removed unused storedelay from align.

---
 src/lsu/align.sv | 10 +++-------
 src/lsu/lsu.sv   |  8 +++-----
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index ad0dbf238..094da4a15 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -52,7 +52,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0]       IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
   output logic [P.XLEN-1:0]       IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
   output logic                    SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic                    SelStoreDelay, //*** this is bad.  really don't like moving this outside
   output logic [P.LLEN*2-1:0]     ReadDataWordSpillAllM,
   output logic                    SpillStallM);
 
@@ -118,20 +117,17 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   always_comb begin
     case (CurrState)
-      STATE_READY: if (ValidSpillM & ~MemRWM[0])  NextState = STATE_SPILL;       // load spill
-                   else if(ValidSpillM)           NextState = STATE_STORE_DELAY; // store spill
+      STATE_READY: if (ValidSpillM)  NextState = STATE_SPILL;       // load spill
                    else                           NextState = STATE_READY;       // no spill
       STATE_SPILL: if(StallM)                     NextState = STATE_SPILL;
                    else                           NextState = STATE_READY;
-      STATE_STORE_DELAY: NextState = STATE_SPILL;
       default:                                    NextState = STATE_READY;
     endcase
   end
 
-  assign SelSpillM = (CurrState == STATE_SPILL | CurrState == STATE_STORE_DELAY);
-  assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
+  assign SelSpillM = CurrState == STATE_SPILL;
+  assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall);
   assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
-  assign SelStoreDelay = (CurrState == STATE_STORE_DELAY);  // *** Can this be merged into the PreLSURWM logic?
   assign SpillStallM = SelSpillE;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 1712cdc19..cf1767f5c 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -142,7 +142,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic [(P.LLEN-1)/8:0] ByteMaskExtendedM;                      // Selects which bytes within a word to write
   logic [1:0]            MemRWSpillM;
   logic                  SpillStallM;
-  logic                  SelStoreDelay;
   
   logic                  DTLBMissM;                              // DTLB miss causes HPTW walk
   logic                  DTLBWriteM;                             // Writes PTE and PageType to DTLB
@@ -168,8 +167,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
                      .MemRWM,
                      .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
                      .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM(LSUWriteDataM[P.LLEN-1:0]), .ByteMaskSpillM,
-                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .ReadDataWordSpillAllM, .SpillStallM,
-                     .SelStoreDelay);
+                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .ReadDataWordSpillAllM, .SpillStallM);
     assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; 
     assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
   end else begin : no_ziccslm_align
@@ -179,7 +177,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign ReadDataWordSpillAllM = DCacheReadDataWordM;
     assign ByteMaskSpillM = ByteMaskM;
     assign MemRWSpillM = MemRWM;
-    assign {SpillStallM, SelStoreDelay} = '0;
+    assign {SpillStallM} = '0;
   end
 
     if(P.ZICBOZ_SUPPORTED) begin : cboz
@@ -333,7 +331,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB),
-        .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), 
+        .CacheRW(CacheRWM), 
         .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
         .CacheWriteData(LSUWriteDataM), .SelHPTW,