From a1eccf37dcbcd757a379637ffd4cdb02cd1584fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Mar 2023 04:33:14 -0700 Subject: [PATCH] Fix Issue 145 --- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- src/mmu/mmu.sv | 2 +- src/mmu/pmpadrdec.sv | 8 ++++---- src/mmu/pmpchecker.sv | 2 +- src/privileged/csr.sv | 2 +- src/privileged/csrm.sv | 6 +++--- src/privileged/privileged.sv | 2 +- src/wally/wallypipelinedcore.sv | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index d8d48cbf4..f753dcd17 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -90,7 +90,7 @@ module ifu ( output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit output logic InstrAccessFaultF, // Instruction access fault output logic ICacheAccess, // Report I$ read to performance counters output logic ICacheMiss // Report I$ miss to performance counters diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 628c85bbd..edb3a93d3 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -88,7 +88,7 @@ module lsu ( output logic ITLBWriteF, // Write PTE to ITLB output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit ); logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index e3cd8031e..4accf0cbc 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -56,7 +56,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( // PMA checker signals input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses ); logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 5f666eeaf..5e63e7c65 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -35,7 +35,7 @@ module pmpadrdec ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic [7:0] PMPCfg, - input logic [`XLEN-1:0] PMPAdr, + input logic [`PA_BITS-3:0] PMPAdr, input logic PAgePMPAdrIn, output logic PAgePMPAdrOut, output logic Match, Active, @@ -60,7 +60,7 @@ module pmpadrdec ( // Top-of-range (TOR) // Append two implicit trailing 0's to PMPAdr value - assign CurrentAdrFull = {PMPAdr[`PA_BITS-3:0], 2'b00}; + assign CurrentAdrFull = {PMPAdr, 2'b00}; assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison assign PAgePMPAdrOut = ~PAltPMPAdr; assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; @@ -69,10 +69,10 @@ module pmpadrdec ( logic [`PA_BITS-1:0] NAMask, NABase; assign NAMask[1:0] = {2'b11}; - assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0]; + assign NAMask[`PA_BITS-1:2] = (PMPAdr + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr; // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. // This assumes we're using at least an NA4 region, but works for any size NAPOT region. - assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. + assign NABase = {(PMPAdr & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 828747e24..b75824257 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -42,7 +42,7 @@ module pmpchecker ( // keyword, the compiler warns us that it's interpreting the signal as a var, // which we might not intend. input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input logic ExecuteAccessF, WriteAccessM, ReadAccessM, output logic PMPInstrAccessFaultF, output logic PMPLoadAccessFaultM, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 06762e6db..d64381c11 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -85,7 +85,7 @@ module csr #(parameter output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic [1:0] STATUS_FS, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], output logic [2:0] FRM_REGW, // output logic [`XLEN-1:0] CSRReadValW, // value read from CSR diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index cbeab5fdd..9fd46b2e2 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -85,7 +85,7 @@ module csrm #(parameter output logic [`XLEN-1:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic WriteMSTATUSM, WriteMSTATUSHM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM ); @@ -113,7 +113,7 @@ module csrm #(parameter assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01); assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i]; - flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); + flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]); if (`XLEN==64) begin assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]); @@ -171,7 +171,7 @@ module csrm #(parameter entry = '0; IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry - CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]; + CSRMReadValM = {{(`XLEN-(`PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin if (`XLEN==64) begin entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64 diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 293fc4b31..2bf0dee4c 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -81,7 +81,7 @@ module privileged ( output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration entries to MMU - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU output logic [2:0] FRM_REGW, // FPU rounding mode // PC logic output in privileged unit output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 601668627..a28c80c9d 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -110,7 +110,7 @@ module wallypipelinedcore ( logic SelHPTW; // PMA checker signals - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; // IMem stalls